Senior ASIC Design Engineer

Nvidia

Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
88 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $187k
This role $216k
$127k most similar roles pay here $279k

This role pays more than 78% of similar roles. Most pay $158,512–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer

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NVIDIA is hiring a Senior ASIC Design Engineer to join its GPU Design team, where you will implement high-performance and efficient RTL designs to meet stringent specifications. Your responsibilities include analyzing architectural trade-offs, crafting micro-architectures, and collaborating with various teams such as architects, verification specialists, and back-end engineers on IPs like work schedulers and DMA engines. Ideal candidates have a Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science, along with 8+ years of relevant work experience in micro-architecture and RTL development using Verilog. Strong skills in ASIC design flow, digital systems, VLSI design, and computer architecture are essential, as is proficiency in C/C++, Python, or Perl. This role demands creativity, autonomy, and a passion for tackling complex challenges in the cutting-edge semiconductor industry.

Skills

Verilog RTL C C++ Python Perl VLSI Computer_Architecture Digital_Systems Logic_Synthesis Timing_Analysis

What you'll do

  • Implement high-performance, area-efficient RTL designs to meet project specifications.
  • Analyze architectural trade-offs considering features and system limitations.
  • Craft micro-architecture and implement in RTL, ensuring full verification and clean synthesis/timing.
  • Work on IPs such as GPU work schedulers, time distribution systems, interrupt controllers, and DMA engines.
  • Architect features aiding silicon debug and support post-silicon validation activities.

What we're looking for

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or Computer Science required.
  • At least 8 years of experience in ASIC design and RTL development.
  • Expertise in micro-architecture and Verilog for arbiters, scheduling, synchronization, bus protocols, interconnect networks, and caches.
  • Proficient understanding of the entire ASIC design flow including verification and timing analysis.
  • Strong interpersonal skills and ability to collaborate across multiple engineering teams.
  • Experience with C/C++, Python, or Perl programming languages.

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