Senior ASIC Design Engineer

Nvidia

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
8 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $216k
$131k $279k
below market most similar roles pay here above market

This role pays more than 83% of similar roles. Most pay $166,538–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer

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As a Senior ASIC Design Engineer within the GPU Design team, you will implement, document, and deliver high-performance, area-efficient, and power-efficient RTL to meet specific design targets. Your daily responsibilities include analyzing architectural trade-offs, crafting micro-architecture, and delivering fully verified, synthesis and timing clean designs. You will collaborate with architects and various verification, synthesis, and back-end teams to develop critical IPs such as work schedulers, time distribution systems, interrupt controllers, and DMA engines. The role requires proficiency in Verilog for RTL development, along with experience in arbiters, scheduling, synchronization, bus protocols, interconnect networks, and caches. You must possess a deep understanding of ASIC design flows, logic synthesis, timing analysis, digital systems, VLSI design, computer architecture, and computer arithmetic, while utilizing C/C++, Python, or Perl.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic

What you'll do

  • Implement, document, and deliver high-performance, area, and power-efficient RTL to meet design targets.
  • Analyze architectural trade-offs based on features, performance requirements, and system limitations.
  • Craft micro-architecture and implement it in RTL to produce a fully verified, synthesis/timing clean design.
  • Develop various IPs including GPU work schedulers, time distribution systems, interrupt controllers, and DMA engines.
  • Architect features to facilitate silicon debugging and support post-silicon validation activities.
  • Coordinate with architects, verification teams, and back-end teams to complete design tasks.

What we're looking for

  • Bachelor's Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
  • 8+ years of meaningful work experience.
  • Experience in micro-architecture and RTL development (Verilog) focused on arbiters, scheduling, synchronization, bus protocols, interconnect networks, and/or caches.
  • Great understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.
  • Strong interpersonal skills and an excellent teammate.
  • Strong C/C++, Python, or Perl skills (preferred).
  • Good debugging and analytical skills (preferred).

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