Senior ASIC Design Engineer

Nvidia

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
28 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $216k
$132k most similar roles pay here $279k

This role pays more than 80% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer

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As a Senior ASIC Design Engineer on the GPU Design team, you will implement, document, and deliver high-performance, area-efficient, and power-efficient RTL to meet specific design targets. Your daily responsibilities include analyzing architectural trade-offs based on performance requirements, crafting micro-architecture, and delivering fully verified designs that are synthesis and timing clean. You will work on a diverse range of IPs including GPU work schedulers, time distribution systems, interrupt controllers, and DMA engines while architecting features to support post-silicon validation. The role requires expertise in Verilog for RTL development, as well as experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks, and caches. You should possess a deep understanding of ASIC design flows, logic synthesis, and timing analysis. Proficiency in C/C++, Python, or Perl is also valued to support your technical work on complex SoC and GPU designs.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis VLSI Computer Architecture C++ Python Perl Bus Protocols Interconnect Networks DMA Engines Digital Systems

What you'll do

  • Implement and document high-performance, area, and power-efficient RTL to meet design targets.
  • Analyze architectural trade-offs based on features, performance requirements, and system limitations.
  • Craft micro-architecture and deliver fully verified, synthesis/timing clean designs.
  • Develop a broad range of IPs including work schedulers, time distribution systems, interrupt controllers, and DMA engines.
  • Architect specific features to facilitate silicon debug and post-silicon validation activities.
  • Coordinate with cross-functional teams across the design flow to ensure successful project completion.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
  • 8+ years of meaningful work experience.
  • Experience in micro-architecture and RTL development using Verilog.
  • Expertise in arbiters, scheduling, synchronization, bus protocols, interconnect networks, and/or caches.
  • Strong understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Required exposure to Digital systems, VLSI design, Computer Architecture, and Computer Arithmetic.
  • Proficiency in C/C++, Python, or Perl is preferred.
  • Strong interpersonal skills and excellent teamwork abilities.

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