ASIC Design Engineer, Fabric/Interconnect

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $129,300–$194,700 / yr
Posted: 12 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k

This role $162k

$117k $248k

below market most similar roles pay here above market

This role pays less than 78% of similar roles. Most pay $168,425–$224,075 — the blue band above. At the midpoint, this role pays about $162k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3544 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2734 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Fabric/Interconnect

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The ASIC Design Engineer – Fabric/Interconnect joins the hardware team to design and integrate coherent and non-coherent fabrics into subsystems or SoCs. The role involves owning all aspects of RTL development, including design, templating, scripting, and RTL generation. Key responsibilities include integrating common shared IP blocks, optimizing memories and hard macros, and collaborating with front-end synthesis, STA, power, performance, and functional verification teams to ensure timing and quality. The position requires deep knowledge of on-chip interconnect architectures like NoC topologies, crossbars, and arbitration, as well as cache coherency protocols such as MESI, MOESI, and directory-based coherence. Candidates must utilize front-end tools for lint, CDC, and synthesis to deliver sophisticated designs for low power applications within a complex system memory hierarchy.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

RTL NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration SoC Front-end Synthesis

What you'll do

Design and integrate coherent and non-coherent fabrics into subsystems or SoCs.
Own all aspects of RTL development including design, templating, scripting, and RTL generation.
Integrate common and shared IP blocks to design and optimize required memories and hard macros.
Coordinate with front-end synthesis and STA teams to ensure all block timing requirements are met.
Partner with power, performance, and functional verification teams to ensure high-quality block delivery.
Incorporate proper checks at every stage of the design process to ensure on-time delivery.

What we're looking for

Bachelor of Science degree.
Experience designing and integrating coherent and non-coherent fabrics into subsystems or SoCs.
Knowledge of on-chip interconnect architectures including NoC topologies, crossbars, and arbitration.
Ability to own all aspects of RTL development including design, templating, scripting, and RTL generation.
Knowledge of cache coherency protocols and memory hierarchy (preferred).
Track record of delivering large, sophisticated designs for low power applications (preferred).
Experience working with synthesis, power, performance, and verification teams (preferred).
Familiarity with front-end tools including lint, CDC, and synthesis (preferred).