Senior ASIC Design Engineer, DFT

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $216k
$135k $278k
below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $172,000–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1626 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1115 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer, DFT

Role Posting Log in to save

The Senior ASIC Design Engineer - DFT will join the DFX Methodology Team to shape the architecture, design, implementation, and verification of DFT IPs for next-generation SoC products. This role involves owning the architecture and design of fuse controllers and other DFT IPs while developing scalable methodologies across the full silicon lifecycle from pre-silicon to post-silicon. Key responsibilities include defining feature sets with architects, creating test plans for full-chip verification, and supporting post-silicon bring-up and debug. Candidates must possess expertise in SoC architecture, RTL design, and verification using Verilog, with UVM experience as a plus. Required skills include proficiency in Python, Perl, or Tcl, along with knowledge of clocking, STA, place and route, and power optimization to solve complex semiconductor chip challenges.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis

What you'll do

  • Own the architecture and design of fuse controllers and other DFT IPs for next-generation SoC products.
  • Develop, deploy, and enhance DFT methodologies to ensure scalability for future product needs.
  • Define and align feature sets by coordinating with architects, platform, and software teams.
  • Partner with design, verification, synthesis, and backend teams to ensure cohesive hardware integration.
  • Create and execute test plans to support functional and DFT full-chip verification.
  • Support post-silicon bring-up and validation efforts, including debugging and issue resolution.
  • Mentor junior engineers on test design strategies regarding cost, quality, and performance trade-offs.

What we're looking for

  • BS/MS in Electrical or Computer Engineering or equivalent experience in a related domain.
  • 8+ years of hands-on experience in SoC architecture, RTL design, and verification.
  • Strong proficiency in micro-architecture and RTL development using Verilog.
  • Experience in DFT design, methodology, and implementation.
  • Familiarity with clocking, STA, place & route, and power optimization.
  • Experience in post-silicon bring-up on ATE, including pattern formats, test program development, and failure analysis.
  • Proficiency in scripting languages such as Python, Perl, or Tcl.
  • Experience with UVM-based verification environments (preferred); experience designing fuse, eFuse, or on-chip security blocks (preferred).

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