Senior ASIC Design Engineer, DFX

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
7 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $216k
$137k most similar roles pay here $278k

This role pays more than 76% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer, DFX

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As a Senior ASIC Design Engineer - DFX on the DFX Methodology Team, you will shape the architecture, design, implementation, and verification of DFT IPs for next-generation SoC products. You will own the architecture of fuse controllers and other DFT IPs while developing scalable methodologies across the full silicon lifecycle from pre-silicon to post-silicon. Your daily work involves collaborating with architects, platform, and software teams to align feature sets, partnering with synthesis and timing teams for integration, and executing test plans for full-chip verification. You will also support post-silicon bring-up and mentor junior engineers on test design strategies. Required skills include expertise in SoC architecture, RTL design using Verilog, and DFT methodology. You should be proficient in Python, Perl, or Tcl, with knowledge of clocking, STA, and power optimization for complex semiconductor chips.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis

What you'll do

  • Own the architecture and design of fuse controllers and other DFT IPs for next-generation SoC products.
  • Develop, deploy, and enhance DFT methodologies to ensure scalability for future product needs.
  • Define and align feature sets by collaborating with architects, platform, and software teams.
  • Coordinate with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
  • Create and execute test plans to support both functional and DFT full-chip verification.
  • Support post-silicon bring-up and validation efforts including debug and issue resolution.
  • Mentor junior engineers on test design strategies regarding cost, quality, and performance trade-offs.

What we're looking for

  • Bachelor's degree with 8+ years of experience or a Master's degree in Electrical Engineering or related field with 6+ years of experience.
  • At least 5 years of hands-on experience in SoC architecture, RTL design, and verification.
  • Strong proficiency in micro-architecture and RTL development using Verilog.
  • Deep expertise in DFT design, methodology, and implementation.
  • Familiarity with clocking, STA, place & route, and power optimization.
  • Experience in post-silicon bring-up on ATE including pattern formats, test program development, and failure analysis.
  • Proficiency in scripting languages such as Python, Perl, or Tcl.
  • Excellent communication skills and a collaborative mindset to solve complex technical challenges.

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