ASIC Design Verification Engineer

Cisco

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Employment
Full-time
Posted
13 days ago
Freshness
Confirmed live today
Closes
Dec 18, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $189k
$136k $235k
below market most similar roles pay here above market

This role pays more than 55% of similar roles. Most pay $162,000–$217,525 — the blue band above. At the midpoint, this role pays about $189k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

Role Posting Log in to save

ASIC Design Verification Engineer The ASIC Design Verification Engineer joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. This role involves architecting and maintaining block, cluster, and top-level design verification infrastructure while building environments from scratch. Key responsibilities include creating comprehensive test plans using constraint-random and directed stimulus, ensuring functional coverage, and qualifying RTL designs through Gate Level Simulations on netlists. The engineer will collaborate with architects and software teams to debug issues during post-silicon bring-up and support testing in emulation environments. Required skills include SystemVerilog, UVM methodology, and scripting with Perl or Python. Preferred experience includes forwarding logic, P4, and emulation platforms like Veloce or Palladium. Domain knowledge in protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP is also required.

Skills

System Verilog UVM Python Perl ASIC Design Verification Gate Level Simulation Veloce Palladium Zebu HAPS VC Formal IEV P4 PCIe CXL Ethernet RDMA DDR TCP

What you'll do

  • Architect, develop, and maintain block, cluster, and top-level Design Verification environment infrastructure.
  • Build Design Verification environments from scratch for both block and cluster levels.
  • Develop and enhance test plans using constraint-random and directed stimulus.
  • Implement and review code and functional coverage to ensure comprehensive verification.
  • Qualify RTL design by running Gate Level Simulations on netlists.
  • Debug issues during post-silicon bring-up and integration with designers and software teams.
  • Support design testing within emulation environments.

What we're looking for

  • Bachelor's degree in Computer, Electrical, or Electronics Engineering plus 5 years of relevant technical experience.
  • Master's degree in a related field plus 3 years of relevant technical experience.
  • Experience in ASIC design and verification.
  • Experience in System Verilog or UVM methodology.
  • Experience building reusable and scalable test benches from scratch.
  • Experience with scripting using Perl and/or Python.
  • Experience with forwarding logic, parsers, or P4 (preferred).
  • Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS (preferred).

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