ASIC Design Verification Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Irvine, CAAndover, MABroomfield, CO
Employment
Full-time
Posted
12 days ago
Freshness
Confirmed live today
Closes
Apr 8, 2027
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $190k
$136k $235k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $162,000–$217,525.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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The ASIC Design Verification Engineer joins a stable team developing silicon products for Ethernet systems in the Cloud to accelerate AI/ML workflows. This role involves verifying new designs that evolve rapidly in a dynamic market, focusing on high throughput Ethernet solutions that prioritize performance and power efficiency. The engineer will work with worldwide design and architecture teams to handle all aspects of Design Verification, including opportunities for technical leadership. Key responsibilities include using constrained random verification methodologies to drive completion via coverage closure. Required technical skills include System Verilog and UVM, with specific experience in TB structures, Class, and SVA. Proficiency with VCS, Incisive, and scripting languages like Python or Perl is also required. The role addresses the technical challenge of delivering unprecedented performance for cloud infrastructure.

Skills

System Verilog UVM Constrained Random Verification VCS Incisive Python Perl SVA OOP Coverage Closure Ethernet AI/ML Scripting

What you'll do

  • Perform constrained random design verification for high-throughput Ethernet solutions.
  • Develop verification environments using SystemVerilog and UVM methodologies.
  • Drive verification completion through rigorous coverage closure.
  • Verify new silicon designs for AI/ML workflow acceleration.
  • Utilize VCS and Incisive tools for design verification tasks.
  • Write scripts in Python or Perl to support verification workflows.
  • Provide technical leadership on all aspects of the design verification process.

What we're looking for

  • Bachelors degree and 12+ years of related experience.
  • Masters degree and 10+ years of related experience.
  • PhD and 3+ years of related experience.
  • Experience with constrained random verification methodologies and driving completion via coverage closure.
  • Skills with SystemVerilog and UVM (preferred).
  • Proficiency with OOP tools and languages including SystemVerilog (TB structures, SVA, etc.) and UVM.
  • Experience with VCS and Incisive.
  • Scripting skills in Python or Perl (preferred).

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