ASIC Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Irvine, CASan Jose, CARichmond, BC, Canada
Salary
$121,900–$195,000 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Apr 8, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $158k
$109k $243k
below market most similar roles pay here above market

This role pays less than 81% of similar roles. Most pay $167,900–$224,075 — the blue band above. At the midpoint, this role pays about $158k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · ASIC Design Engineer

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The ASIC Design Engineer will join a skilled engineering group focused on developing next-generation high throughput Ethernet products for datacenter and cloud operators. This role involves working with a worldwide design and architecture team to create new designs for PCIe and other host interfaces. The engineer will be involved in all aspects of front end design, including architecture definition, RTL coding, simulation, verification, synthesis, timing closure, and silicon validation. Candidates must possess a BSEE with 8+ years of experience or an MSEE with 6+ years of experience in high speed communication chip architecture. Required technical skills include proficiency in Python or Perl scripting and deep knowledge of ethernet controllers or PCIe. The work addresses the need for high performance and power efficiency in AI and cloud mega data centers.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design RTL Design Ethernet PCIe Python Perl Simulation Verification Synthesis Timing Closure Silicon Validation Architecture Definition high speed communication front end design

What you'll do

  • Develop next-generation high-throughput Ethernet products for datacenter and cloud operators.
  • Design and develop PCIe and other host interfaces for high-speed communication chips.
  • Perform all aspects of front-end design for new world-class devices.
  • Execute the full ASIC design process including architecture definition and RTL coding.
  • Conduct simulation, verification, synthesis, and timing closure for silicon designs.
  • Perform silicon validation to ensure product performance and power efficiency.
  • Create technical documentation and use Python or Perl for scripting tasks.

What we're looking for

  • BSEE with 8+ years of industry experience in high speed communication chip architecture and RTL design.
  • MSEE with 6+ years of industry experience in high speed communication chip architecture and RTL design.
  • Hands-on experience in the ASIC design process including architecture definition, RTL coding, simulation, synthesis, timing closure, and silicon validation.
  • Strong communication and documentation skills.
  • Scripting skills using either Python or Perl.
  • Strong knowledge and background in either ethernet controller or PCIe (preferred).
  • Ability to work in Irvine, CA, San Jose, or Richmond, BC, Canada.

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