ASIC Design and Integration Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 7 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $164,938–$219,500 — the blue band above. At the midpoint, this role pays about $255k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer

Role Posting Log in to save

The ASIC Design and Integration Engineer joins a complex hardware team to craft upcoming products by managing various aspects of SOC design. The role involves writing microarchitecture and design specifications, designing and debugging complex logic designs, and integrating complex IPs into the SOC. Key responsibilities include supporting front-end integration activities such as Lint, CDC, RDC, Synthesis, and ECO while collaborating with specialists across Verification, Emulation, STA, and Physical Design teams. Candidates must utilize Verilog RTL logic design, low-power methodologies, and scripting languages like Perl, Python, or Tcl. The position requires expertise in multiple clock domains, asynchronous interfaces, and power/clock management design. This role solves technical challenges in system architecture and CPU and IP integration to ensure high-quality hardware performance.

Skills

Verilog RTL ASIC Design SOC Design CDC Lint Synthesis ECO Python Perl Tcl STA Physical Design GenAI System Architecture

What you'll do

Write microarchitecture and design specifications for SOC components.
Design, implement, and debug complex logic designs.
Integrate complex IPs into the SOC.
Support front-end integration activities including Lint, CDC, RDC, Synthesis, and ECO.
Manage power and clock management design for CPU and IP integration.
Convert technical specifications into functional hardware designs.
Handle multiple clock domains and asynchronous interfaces.

What we're looking for

BS degree in a relevant field.
Minimum of 10 years of relevant industry experience.
Verilog RTL logic design experience (preferred).
Proven experience and solid knowledge in CDC and low-power methodologies (preferred).
Familiarity with scripting languages like Perl, Python, or Tcl (preferred).
Familiarity with GenAI tools and workflows (preferred).
Experience writing specifications and converting them into design (preferred).
Experience with multiple clock domains and asynchronous interfaces (preferred).

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