Senior ASIC Design Engineer

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
80 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 52% of similar roles. Most pay $158,512–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer

NVIDIA seeks a Senior ASIC Design Engineer to join its globally recognized team dedicated to pushing the boundaries of SoC and GPU design. This role involves documenting, implementing, and delivering high-performance, area-efficient RTL designs that meet stringent specifications through advanced CAD tools and semiconductor technologies. Responsibilities include architecture design, RTL development, synthesis, and verification using sophisticated methodologies while collaborating with multiple teams across remote locations. Ideal candidates hold a Bachelors or Masters Degree in relevant fields, have over five years of experience in VLSI and Computer Architecture, and expertise in Verilog/SystemVerilog, Perl/Python scripting, logic synthesis, and timing analysis. Familiarity with design verification tools like VCS, debug tools such as Verdi/GDB, and test bench environments for unit/system level verification is essential, along with strong interpersonal skills to work effectively on diverse teams.

What you'll do

  • Document and implement high-performance, area-efficient RTL designs.
  • Design and synthesize logic using advanced CAD tools and semiconductor technologies.
  • Define verification scope and develop verification infrastructure for complex SoCs.
  • Participate in architecture and micro-architecture design to meet performance targets.
  • Collaborate with multiple ASIC development teams on global projects.

What we're looking for

  • 5+ years of relevant ASIC design experience.
  • Expertise in VLSI and Computer Architecture with proficiency in Verilog or System Verilog.
  • Experience in logic synthesis, timing analysis, and embedded processor development.
  • Proficiency in Perl/Python scripting for hardware engineering tasks.
  • Hands-on experience with advanced verification tools and methodologies.
  • Strong collaboration skills for working with remote teams globally.

More like this

Similar roles

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 88 days ago $168,000$264,500
Verilog RTL C C++ Python Perl VLSI Computer_Architecture Digital_Systems Logic_Synthesis Timing_Analysis
Hybrid

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 17 days ago $168,000$264,500
Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels

Senior ASIC Design Engineer - Hardware

Nvidia

Santa Clara, CA 148 days ago $136,000$218,500
Verilog RTL Python Perl C C++ PCI-Express CXL ASIC VLSI Digital systems Computer Architecture CMOS transistors and circuits DFT timing analysis floor-planning ECO bring-up & lab debug arbiters synchronization bus protocols interconnect networks caches

Senior ASIC Verification Engineer

Nvidia

Austin, TX 17 days ago $136,000$218,500
SystemVerilog UVM Perl Python dc_shell VCS Debussy GDB CI/CD ASIC RTL Object-Oriented Programming
Hybrid

Senior ASIC Verification Engineer

Nvidia

Santa Clara, CA 67 days ago $136,000$218,500
SystemVerilog C++ UVM VCS Debussy GDB Python CI/CD Git Linux ASIC GPU Computer Architecture Digital Design Processor Pipeline Verification