Senior ASIC Design Engineer

Nvidia

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Employment
Full-time
Posted
23 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $192k
$139k $240k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,500–$216,250.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1531 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1104 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer

Role Posting Log in to save

The Senior ASIC Design Engineer joins a global team to design and implement leading SoCs and GPUs for consumer graphics, self-driving cars, and artificial intelligence. The role involves documenting, implementing, and delivering high-performance, area-efficient RTL to meet specific design targets. Key responsibilities include architecture and micro-architecture design, RTL design, synthesis, and logic and timing verification using pioneering CAD tools and semiconductor process technologies. The engineer will also define verification scopes and support infrastructure development. Required expertise includes Verilog, SystemVerilog, and scripting in Perl or Python. Candidates must possess a hardware engineering background in VLSI and Computer Architecture, with experience in logic synthesis, timing analysis, and tools like VCS, Verdi, and GDB. The position requires collaborating with remote teams to solve complex computing platform problems.

What does a ASIC Design Engineer earn in California?

Median $214000 from 53 postings across 7 companies.

See salary data

Skills

ASIC Design RTL Design Verilog System Verilog Python Perl Logic Synthesis Timing Analysis VLSI Computer Architecture VCS Verdi GDB Functional Coverage Assertion-Based Verification Embedded Processors SoC GPU

What you'll do

  • Document, implement, and deliver high-performance, area-efficient RTL to meet design targets.
  • Perform architecture and micro-architecture design for SoCs and GPUs.
  • Execute RTL design and logic synthesis using pioneering CAD tools.
  • Conduct logic and timing verification using advanced semiconductor process technologies.
  • Define verification scope and support the development of verification infrastructure.
  • Verify designs using sophisticated methodologies including random stimulus and functional coverage.
  • Debug hardware designs using tools like Verdi and GDB.

What we're looking for

  • A Bachelor's or Master's Degree or equivalent experience is required.
  • Candidates must have 5+ years of relevant work experience.
  • Proven hardware engineering background with a concentration in VLSI and Computer Architecture is required.
  • Expertise in Verilog, SystemVerilog, or similar HDL is required.
  • Proficiency in Perl, Python, or similar scripting languages is required.
  • Experience with logic synthesis and timing analysis is required.
  • Experience with design and verification tools like VCS, Verdi, or GDB is required.
  • Experience with embedded processors is a plus (preferred).

Related searches

More Senior ASIC Design Engineer jobs Senior ASIC Design Engineer jobs in Santa Clara All jobs at Nvidia

More like this

Similar roles

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 32 days ago
ASIC Design RTL Design Verilog System Verilog Python C/C++ Perl Logic Synthesis Timing Analysis VCS Debussy GDB Formal Verification Assertion-Based Verification Computer Architecture VLSI Simulation Functional Coverage
5+ yrs exp Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 81 days ago
ASIC Design Verilog System-Verilog RTL Design VLSI Digital Systems Design Computer Architecture Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT Mixed Signal Design Post-Si Bringup Agentic AI flows
3+ yrs exp Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA +1 11 days ago $168,000–$264,500
ASIC Design RTL Verilog Micro-architecture VLSI Logic Synthesis Timing Analysis DFT Computer Architecture PCI-Express CXL Python Perl C/C++ CMOS Post-silicon Validation Floor-planning ECO Bus Protocols Interconnect Networks
8+ yrs exp
Save

Senior ASIC Hardware Design Engineer

Nvidia

Westford, MA 106 days ago
Verilog SystemVerilog RTL ASIC Design VLSI Python Perl Micro-architecture Logic Design Timing Closure Synthesis Digital Systems Hardware Engineering
5+ yrs exp
Save

ASIC Design Engineer

Nvidia

Santa Clara, CA 60 days ago $116,000–$189,750
RTL Design Verilog Microarchitecture Logic Synthesis Timing Analysis Python Perl C/C++ VLSI Design Digital Systems Computer Architecture ASIC Design SoC Post-Silicon Validation Front-end Flow
2+ yrs exp
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 63 days ago $168,000–$264,500
RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic
8+ yrs exp Hybrid
Save