Senior ASIC Design Verification Engineer

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live yesterday
Closes
Nov 20, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $206k
$132k $257k
below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $168,175–$216,250 — the blue band above. At the midpoint, this role pays about $206k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 300 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 223 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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The Senior ASIC Design Verification Engineer joins the Silicon One team to develop revolutionary data center solutions. In this role, you will define, architect, and verify high-performance ASICs and subsystems to meet specific power, performance, and area goals. Your daily responsibilities include building cluster and chip-level verification environments from scratch, developing test plans using constraint-random and directed stimulus, and qualifying RTL designs through Gate Level Simulations with timing annotation. You will also debug issues at the ASIC, software, and systems levels during lab bring-up and post-silicon validation. Required technical skills include OOP concepts, SystemVerilog, UVM methodology, and scripting in Perl or Python. Preferred experience includes forwarding logic, P4, formal verification tools, and protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Skills

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP

What you'll do

  • Drive the definition, architecture, and design of high-performance ASICs and functional areas.
  • Define new verification methodologies and develop reusable code for future projects.
  • Lead design verification efforts by solving block-level and chip-level issues.
  • Architect, develop, and maintain cluster and top-level Design Verification environment infrastructure.
  • Build DV environments from scratch for cluster and chip levels.
  • Develop and enhance test plans using constraint-random and directed stimulus.
  • Ensure comprehensive verification coverage through code and functional coverage implementation.
  • Qualify RTL design by running Gate Level Simulations with timing annotation.

What we're looking for

  • Bachelor's degree in Computer, Electrical, or Electronics Engineering plus 7 years of relevant technical experience.
  • Master's degree plus 4 years of relevant technical experience with a focus on ASIC design and verification.
  • Experience in OOP concepts, SystemVerilog, or UVM methodology.
  • Experience leading verification teams or assignment projects.
  • Experience with scripting using Perl and/or Python.
  • Experience with forwarding logic, parsers, or P4 (preferred).
  • Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS (preferred).
  • Knowledge of formal verification tools or domain knowledge in protocols like PCIe, CXL, Ethernet, RDMA, DDR, or TCP (preferred).

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