ASIC Design and Integration Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$277,600 / yr
Posted: 7 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 68% of similar roles. Most pay $164,938–$220,375 — the blue band above. At the midpoint, this role pays about $214k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · ASIC Design and Integration Engineer

Role Posting Log in to save

The ASIC Design and Integration Engineer joins a complex hardware team to craft upcoming products by managing various aspects of SOC design. The role involves writing microarchitecture and design specifications, designing and debugging complex logic designs, and integrating complex IPs into the SOC. Key responsibilities include supporting front-end integration activities such as Lint, CDC, RDC, Synthesis, and ECO while collaborating with verification, emulation, STA, and physical design teams. Candidates must utilize Verilog RTL logic design, low-power methodologies, and scripting languages like Perl, Python, or Tcl. The position requires expertise in multiple clock domains, asynchronous interfaces, and power/clock management design. This role solves technical challenges in chip development by converting specifications into functional designs and ensuring high quality through cross-functional software and systems collaboration.

Skills

Verilog RTL ASIC Design SOC Design Lint CDC RDC Synthesis ECO STA Physical Design Python Perl Tcl GenAI System Architecture

What you'll do

Write microarchitecture and design specifications for SOC components.
Design, implement, and debug complex logic designs.
Integrate complex IPs into the System on Chip (SOC).
Support front-end integration activities including Lint, CDC, RDC, Synthesis, and ECO.
Manage multiple clock domains and asynchronous interfaces.
Convert high-level specifications into functional RTL designs.
Implement low-power methodologies and power/clock management designs.

What we're looking for

BS degree in a relevant field.
Minimum of 3 years of relevant industry experience.
Verilog RTL logic design experience (preferred).
Proven experience and solid knowledge in CDC and low-power methodologies (preferred).
Familiarity with scripting languages like Perl, Python, or Tcl (preferred).
Familiarity with GenAI tools and workflows (preferred).
Experience writing specifications and converting them into design (preferred).
Experience with multiple clock domains and asynchronous interfaces (preferred).

Similar roles

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 7 days ago $184,700–$324,800

Verilog RTL ASIC Design SOC Design CDC Lint Synthesis ECO Python Perl Tcl STA Physical Design GenAI System Architecture

10+ yrs exp

Save

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 40 days ago $150,400–$277,600

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Formal Verification FPGA Prototyping PCIe CDC RDC LINT LEC Power Optimization Low-Power Design

3+ yrs exp

Save

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 78 days ago $129,300–$194,700

SystemVerilog RTL Design ASIC Design Synthesis Formal Verification Simulation Timing Analysis Power Optimization CDC RDC Micro-architecture PPA

Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 78 days ago

SystemVerilog RTL Design ASIC Design Synthesis Formal Verification Simulation Timing Analysis Power Optimization CDC RDC Micro-architecture PPA

Save

ASIC Design Engineer

Apple Inc

Cupertino, CA 83 days ago $150,400–$277,600

ASIC Design SoC Design Logic Design Lint CDC Synthesis ECO STA Physical Design Power Management Clock Management Python Perl TCL Microarchitecture IP Integration

3+ yrs exp

Save

ASIC Design Engineer

Apple Inc

Cupertino, CA 83 days ago $184,700–$324,800

ASIC Design SoC Design Logic Design Lint CDC Synthesis ECO STA Physical Design Power Management Clock Management Python Perl TCL Microarchitecture IP Integration

10+ yrs exp

Save