Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: ASIC DFT Remove filter Clear all

20 of up to 20 (filtered)

Senior ASIC Design Engineer, DFT

Nvidia

Santa Clara, CA 4 days ago $168,000–$264,500
Actively hiring Confirmed live today Posted this week High trust Above market
DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis
8+ yrs exp Hybrid
Save

ASIC DFT Engineering Technical Leader

Cisco

San Jose, CA +2 5 days ago $186,900–$267,700
Actively hiring Confirmed live today Posted this week High trust Above market
ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation
8+ yrs exp Hybrid
Save

ASIC DFT STA Engineer

Cisco

San Jose, CA 5 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
STA DFT RTL Design CDC RDC SDC Python TCL Perl Makefile Tessent PCIE BIST Scan Shift/Capture Conformal Verification
7+ yrs exp
Save

ASIC DFT Technical Leader

Cisco

San Jose, CA +1 8 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design
10+ yrs exp Hybrid
Save

Senior ASIC DFT DV Engineer

Cisco

San Jose, CA +1 13 days ago $167,700–$245,200
Actively hiring Confirmed live today High trust Competitive pay
System Verilog UVM Python TCL Perl Verdi DVE JTAG MBIST DFT Scan Architecture Boundary Scan ATE post silicon validation
7+ yrs exp Hybrid
Save

ASIC Post silicon DFT Technical Leader

Cisco

Austin, TX +1 14 days ago $177,600–$257,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure
10+ yrs exp Hybrid
Save

Senior ASIC DFT DV Engineer

Cisco

San Jose, CA 14 days ago $167,700–$245,200
Actively hiring Confirmed live today High trust Competitive pay
DFT MBIST ATE Verilog Python TCL Perl DVE Verdi SRAM DRAM Synopsys DesignWare SMS TestMax Mentor Graphics Tessent
7+ yrs exp Hybrid
Save

ASIC DFT DV Technical Leader

Cisco

San Jose, CA 14 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
System Verilog UVM DFT Python TCL Perl Verdi JTAG MBIST Scan Architecture Boundary Scan ATE RTL Physical Design post silicon validation
8+ yrs exp Hybrid
Save

ASIC DFT Technical Leader, CDC

Cisco

San Jose, CA +2 14 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
ASIC RTL CDC RDC SDC VCS SVA SystemVerilog Synthesis Gate Netlists
8+ yrs exp Hybrid
Save

ASIC DFT Engineer

Cisco

San Jose, CA 15 days ago
Actively hiring Confirmed live today High trust
DFT Verilog System Verilog ATPG JTAG Scan BIST VCS TestMax Tetramax Tessent PrimeTime Gate Level Simulation Post-Silicon Validation ATE P1687 Static Timing Analysis RTL EDA Tools
3+ yrs exp Hybrid
Save

ASIC DFT Emulation Technical Lead

Cisco

San Jose, CA 22 days ago $186,900–$267,700
Actively hiring Confirmed live today Trusted Above market
ASIC DFT Emulation Palladium Veloce Zebu Verilog System Verilog C C++ Tcl Python Perl UVM JTAG MBIST Scan Architecture ATPG Post Silicon validation
8+ yrs exp
Save

ASIC DFT Technical Leader

Cisco

San Jose, CA 41 days ago
Actively hiring Confirmed live yesterday Low trust
Verilog System Verilog ATPG JTAG Scan BIST VCS TestMax Tetramax Tessent PrimeTime Gate Level Simulation Static Timing Analysis post silicon validation RTL Physical Design EDA Tools
10+ yrs exp Hybrid
Save

ASIC DFT Technical Leader, MBIST

Cisco

San Jose, CA +1 54 days ago $214,100–$309,800
Actively hiring Confirmed live today High trust Above market
ASIC DFT MBIST Python TCL Perl Verilog System Verilog Synopsys DesignWare SMS TestMax Mentor Graphics Tessent SRAM DRAM
10+ yrs exp Hybrid
Save

Senior ASIC Timing Engineer, DFT

Nvidia

Santa Clara, CA 77 days ago
Actively hiring Confirmed live today Trusted
Static Timing Analysis STA DFT Timing Closure Timing Constraints DFT Logic Serdes iJTAG Scan PD DFX Clocks GPU
5+ yrs exp
Save

ASIC/SOC DFT Engineer

SpaceX

Austin, TX +1 82 days ago
Actively hiring Confirmed live today Low trust
ASIC DFT ATPG Verilog SystemVerilog Python Perl Bash UPF RTL Gate Level Simulation SDF DRC Formal Verification Synthesis Scan Insertion
1+ yrs exp
Save

ASIC/SOC DFT Engineer

SpaceX

Palo Alto, CA +1 82 days ago $135,000–$175,000
Actively hiring Confirmed live today Low trust Below market
ASIC SOC DFT ATPG Verilog SystemVerilog Python Perl Bash csh UPF DRC RTL Gate Level Simulation SDF Formal Verification Synthesis Physical Design
1+ yrs exp
Save

ASIC DFT Technical Leader

Cisco

San Jose, CA +1 84 days ago $186,900–$267,700
Actively hiring Confirmed live today Low trust Above market
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation P1687 EDA Tools
10+ yrs exp Hybrid
Save

Senior ASIC DFT Engineer

SpaceX

Austin, TX +2 151 days ago
Actively hiring Confirmed live today Low trust
ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ ATE Post-Silicon Validation Gate-Level Simulation SDF IEEE 1500 IEEE 1149.1 BIST Scan Insertion Failure Analysis
5+ yrs exp
Save

Senior ASIC DFT Engineer

SpaceX

Irvine, CA +2 151 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ Post-Silicon Validation ATE Teradyne Advantest SDF IEEE 1500 IEEE 1149.1 Scan Insertion BIST
5+ yrs exp
Save

Senior ASIC DFT Engineer

SpaceX

Palo Alto, CA +2 151 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ Post-Silicon Validation ATE Teradyne Advantest SDF Gate-Level Simulation IEEE 1500 IEEE 1149.1 BIST Scan Insertion
5+ yrs exp
Save