Senior ASIC DFT Engineer

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$175,000–$280,000 / yr
Posted
105 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $228k
$140k most similar roles pay here $295k

This role pays more than 80% of similar roles. Most pay $175,000–$224,075 — the shaded band above. At the midpoint, this role pays about $228k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior ASIC DFT Engineer

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As a Sr. ASIC DFT Engineer (Silicon), you will join a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. You will be responsible for implementing and optimizing DFT architectures, including scan insertion, compression logic, memory BIST, and logic BIST using Siemens Tessent tools. Your daily work involves integrating and verifying DFT IPs, running ATPG tools for various fault models, and performing gate-level simulations. You will also create and validate patterns for post-silicon bringup and ATE debug while developing test scripts and automating processes using Perl, Python, Tcl, or C++. The role focuses on solving complex connectivity challenges by ensuring high-performance silicon meets production requirements through advanced techniques like streaming scan networks and low-power DFT. You will work with technologies at 7nm and below to enhance network capabilities.

Skills

DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation

What you'll do

  • Implement and optimize DFT architectures including scan insertion, compression logic, and memory BIST using Siemens Tessent tools.
  • Integrate and verify DFT IPs and fabrics within various subsystems.
  • Run ATPG tools to generate patterns for stuck-at, transition, and path delay fault models.
  • Execute and debug non-timing and SDF annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug during silicon characterization.
  • Develop test scripts and automate processes using Perl, Python, Tcl, or C++.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
  • Experience with Siemens Tessent tools for DFT architectures, including scan insertion, compression, and BIST.
  • Proficiency in developing test scripts and automating processes using Perl, Python, Tcl, or C++.
  • Experience with Automated Test Equipment (ATE) platforms such as Teradyne or Advantest.
  • Knowledge of industry standards for testability like IEEE 1500 and 1687.
  • Ability to perform post-silicon bringup, silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.

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