ASIC DFT STA Engineer

Cisco

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Closes
Dec 18, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k
This role $206k
$138k $264k
below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $177,250–$227,300 — the blue band above. At the midpoint, this role pays about $206k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT STA Engineer

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The ASIC DFT STA Engineer joins the Silicon One development organization to help craft next-generation networking chips. This role involves driving the DFT and quality process through the entire implementation flow and post-silicon validation phases, with additional exposure to physical design signoff activities. The engineer will manage timing constraints, including clock groups, exceptions, and clock exclusivity, while collaborating with cross-functional teams to communicate complex timing data. Required skills include experience with RTL design, CDC/RDC, conformal verification, and SDC development. Candidates must possess programming proficiency in Perl, TCL, Python, or Makefile. Technical expertise with Synopsys TCM/Primetime, Fusion/design Compiler, and Tessent tools is preferred. The work focuses on solving timing closure for DFT modes such as scan shift/capture and BIST within high-performance silicon hardware platforms.

Skills

STA DFT RTL Design CDC RDC SDC Python TCL Perl Makefile Tessent PCIE BIST Scan Shift/Capture Conformal Verification

What you'll do

  • Develop and verify timing constraints for next-generation networking chips.
  • Manage DFT and quality processes through the entire implementation flow.
  • Perform post-silicon validation and physical design signoff activities.
  • Analyze and debug complex timing constraints for DFT modes like scan shift and BIST.
  • Develop and debug SDC files using industry-standard STA tools.
  • Execute RTL design, CDC/RDC, and conformal verification tasks.
  • Write scripts in Perl, TCL, Python, or Makefile to automate design flows.

What we're looking for

  • Bachelor's degree plus 7 years of related experience, Master's plus 4 years, or PhD plus 1 year of related experience.
  • Prior working experience with RTL design, CDC/RDC and conformal verification, and SDC development.
  • Prior working experience in timing constraint development and verification.
  • Prior programming experience with at least 2 of the following: Perl, TCL, Python, or Makefile.
  • Master's degree plus 10 years of relevant experience (preferred).
  • Prior experience debugging and analyzing PCIE, TSMC memory, and DFT mode timing constraints (preferred).
  • Prior experience with SDC debugging, STA tools like Synopsys TCM/Primetime, and synthesis tools like Synopsys Fusion/design Compiler (preferred).
  • Prior experience with Tessent tool for DFT insertion in RTL (preferred).

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