ASIC DFT Technical Leader

Cisco

Confirmed live today Low trust
Closes in 3 days Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TX
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
84 days ago
Freshness
Confirmed live today
Closes
Oct 30, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $227k
$143k $281k
below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $177,250–$231,737 — the blue band above. At the midpoint, this role pays about $227k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader

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The ASIC DFT Technical Leader joins the Common Hardware Group to support the Silicon One development organization. In this role, you will collaborate with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. You will lead the DFT and quality process through the entire implementation flow and post-silicon validation phases, including physical design signoff activities. Key responsibilities involve working with Jtag protocols, Scan and BIST architectures, and ATPG. You will utilize EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime, while performing gate level simulation with VCS. Required skills include Verilog design, System Verilog Logic Equivalency checking, and experience with P1687 and ATE patterns to solve complex networking chip hardware challenges.

Skills

DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation P1687 EDA Tools

What you'll do

  • Drive DFT requirements early in the design cycle by working with front-end RTL and backend physical design teams.
  • Lead the DFT and quality process through the entire implementation flow and post-silicon validation phases.
  • Develop custom DFT logic and integrate IP using Verilog design experience.
  • Perform post-silicon validation and debug using ATE patterns and P1687.
  • Execute gate-level simulation and debugging using VCS and other simulators.
  • Manage DFT CAD development including test architecture, methodology, and infrastructure.
  • Conduct test static timing analysis and logic equivalency checking using System Verilog.
  • Oversee physical design signoff activities for next-generation networking chips.

What we're looking for

  • Bachelor's or Master's Degree in Electrical or Computer Engineering required.
  • At least 10 years of experience in the field required.
  • Experience in DFT, test, and silicon engineering trends required.
  • Experience with Jtag protocols, Scan, and BIST architectures required.
  • Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime required.
  • Experience with Gate level simulation and debugging with VCS or other simulators required.
  • Post-silicon validation and debug experience with ATE patterns and P1687 required.
  • Verilog design experience, DFT CAD development, and System Verilog Logic Equivalency checking (preferred).

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