ASIC DFT Technical Leader

Cisco

Confirmed live yesterday Trusted

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $186,900–$267,700 / yr
Posted: 38 days ago
Freshness: Confirmed live yesterday
Closes: Oct 2, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $227k

$143k most similar roles pay here $281k

This role pays more than 75% of similar roles. Most pay $177,250–$227,300 — the shaded band above. At the midpoint, this role pays about $227k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader

Role Posting Log in to save

As an ASIC DFT Technical Leader within the Silicon One development organization, you will join the Common Hardware Group to develop next-generation networking chips. You will collaborate with front-end RTL and back-end physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. Your daily responsibilities include leading the DFT and quality process through implementation flows and post-silicon validation phases, including exposure to physical design signoff activities. The role requires expertise in Jtag protocols, Scan and BIST architectures, ATPG, and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime. You will utilize Verilog for custom logic, perform gate-level simulation with VCS, and manage post-silicon validation using ATE patterns and P1687. Key skills include SystemVerilog Logic Equivalency checking, Static Timing Analysis, and developing DFT CAD infrastructure.

Skills

DFT Scan BIST JTAG ATPG TestMax Tetramax Tessent PrimeTime VCS Verilog System Verilog Static Timing Analysis Post-silicon Validation ATE P1687 RTL

What you'll do

Drive DFT requirements early in the design cycle by collaborating with front-end RTL and back-end physical design teams.
Lead the DFT and quality process through the entire implementation flow and post-silicon validation phases.
Manage physical design signoff activities for next-generation networking chips.
Develop custom DFT logic and integrate specialized IP into the chip architecture.
Perform gate-level simulation and debug using tools like VCS.
Execute post-silicon validation and debugging using ATE patterns and P1687 standards.
Conduct static timing analysis and verify test-timing of the design.

What we're looking for

Bachelor's or Master's Degree in Electrical or Computer Engineering.
At least 10 years of experience in the field.
Experience with DFT, test, and silicon engineering trends.
Experience with Jtag protocols, Scan, BIST architectures, memory BIST, and boundary scan.
Experience with ATPG and EDA tools including TestMax, Tetramax, Tessent, and PrimeTime.
Experience with gate level simulation and debugging using VCS or other simulators.
Post-silicon validation and debug experience with ATE patterns and P1687.
Verilog design experience for custom DFT logic and IP integration.

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