ASIC DFT Emulation Technical Lead

Cisco

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
22 days ago
Freshness
Confirmed live today
Closes
Dec 15, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $227k
$141k $281k
below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $177,250–$232,412 — the blue band above. At the midpoint, this role pays about $227k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · ASIC DFT Emulation Technical Lead

Role Posting Log in to save

ASIC DFT Emulation Technical Lead The ASIC DFT Emulation Technical Lead joins the Common Hardware Group to drive the DFT emulation strategy for Silicon One. This role involves architecting state-of-the-art emulation environments, leading pre-silicon test plan execution, and validating complex scan, MBIST, and JTAG architectures. The successful candidate will troubleshoot critical issues and ensure high-quality post-silicon pattern conversion by partnering with front-end RTL, physical design, and ATPG teams. Key responsibilities include ensuring seamless silicon bring-up and optimal test coverage for next-generation hardware platforms. Required technical skills include experience with Palladium, Veloce, or Zebu platforms, as well as Verilog, SystemVerilog, C/C++, and scripting in Tcl, Python, or Perl. The role focuses on solving complex hardware testing problems within the unified silicon architecture for switching and routing products.

Skills

ASIC DFT Emulation Palladium Veloce Zebu Verilog System Verilog C C++ Tcl Python Perl UVM JTAG MBIST Scan Architecture ATPG Post Silicon validation

What you'll do

  • Drive the DFT emulation strategy for Silicon One hardware.
  • Architect state-of-the-art emulation environments on Palladium, Veloce, or Zebu platforms.
  • Lead pre-silicon test plan execution and validation.
  • Validate complex scan, MBIST, and JTAG architectures.
  • Troubleshoot critical issues with front-end RTL, physical design, and ATPG teams.
  • Ensure high-quality post-silicon pattern conversion.
  • Guarantee seamless silicon bring-up and optimal test coverage for next-generation platforms.

What we're looking for

  • Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
  • Prior emulation experience on platforms such as Palladium, Veloce, or Zebu with compilation and debug.
  • Prior experience with Verilog and System Verilog.
  • Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.
  • Prior experience defining DFT Emulation strategy (preferred).
  • Prior experience with JTAG protocol, scan architecture, MBIST and boundary scan (preferred).
  • UVM and advanced System Verilog knowledge (preferred).
  • Post Silicon validation and/or debugging experience (preferred).

Related searches

More ASIC DFT Emulation Technical Lead jobs ASIC DFT Emulation Technical Lead jobs in San Jose All jobs at Cisco

More like this

Similar roles

ASIC DFT DV Technical Leader

Cisco

San Jose, CA 14 days ago $186,900–$267,700
System Verilog UVM DFT Python TCL Perl Verdi JTAG MBIST Scan Architecture Boundary Scan ATE RTL Physical Design post silicon validation
8+ yrs exp Hybrid
Save

ASIC DFT Technical Leader

Cisco

San Jose, CA +1 8 days ago $186,900–$267,700
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design
10+ yrs exp Hybrid
Save

ASIC DFT Technical Leader

Cisco

San Jose, CA +1 84 days ago $186,900–$267,700
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation P1687 EDA Tools
10+ yrs exp Hybrid
Save

ASIC DFT Technical Leader

Cisco

San Jose, CA 41 days ago
Verilog System Verilog ATPG JTAG Scan BIST VCS TestMax Tetramax Tessent PrimeTime Gate Level Simulation Static Timing Analysis post silicon validation RTL Physical Design EDA Tools
10+ yrs exp Hybrid
Save

ASIC Post silicon DFT Technical Leader

Cisco

Austin, TX +1 14 days ago $177,600–$257,400
ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure
10+ yrs exp Hybrid
Save

ASIC DFT Engineering Technical Leader

Cisco

San Jose, CA +2 5 days ago $186,900–$267,700
ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation
8+ yrs exp Hybrid
Save