ASIC DFT Emulation Technical Lead

Cisco

Confirmed live yesterday High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Oct 20, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $227k
$141k most similar roles pay here $281k

This role pays more than 75% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $227k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC DFT Emulation Technical Lead

Role Posting Log in to save

As an ASIC DFT Emulation Technical Lead within the Common Hardware Group, you will drive the DFT emulation strategy for Silicon One. You will architect state-of-the-art emulation environments, lead pre-silicon test plan execution, and validate complex scan, MBIST, and JTAG architectures on Palladium, Veloce, or Zebu platforms. Collaborating with front-end RTL, physical design, and ATPG teams, you will troubleshoot critical issues to ensure high-quality post-silicon pattern conversion and optimal test coverage for next-generation hardware platforms. The role requires proficiency in Verilog, SystemVerilog, C/C++, and scripting using Tcl or Python/Perl. You will apply expertise in JTAG protocols, scan architecture, and boundary scan while utilizing UVM and advanced SystemVerilog knowledge to solve complex technical challenges within the silicon and networking hardware domain for enterprise and service provider infrastructure.

Skills

DFT Emulation Palladium Veloce Zebu Verilog System Verilog C C++ Tcl Python Perl JTAG MBIST Scan Architecture Boundary Scan UVM ATPG

What you'll do

  • Drive the DFT emulation strategy for Silicon One products.
  • Architect state-of-the-art emulation environments on platforms like Palladium, Veloce, or Zebu.
  • Lead pre-silicon test plan execution and validation of scan, MBIST, and JTAG architectures.
  • Troubleshoot critical issues with front-end RTL, physical design, and ATPG teams.
  • Ensure high-quality post-silicon pattern conversion for complex ASICs.
  • Guarantee seamless silicon bring-up and optimal test coverage across next-generation hardware platforms.

What we're looking for

  • Bachelor's degree plus 8 years of related experience, Master's plus 6 years, or PhD plus 3 years.
  • Experience with emulation on platforms such as Palladium, Veloce, or Zebu including compilation and debug.
  • Proficiency in Verilog and System Verilog.
  • Proficiency in C/C++ and scripting skills using Tcl, Python, or Perl.
  • Experience defining DFT Emulation strategy.
  • Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan.
  • UVM and advanced System Verilog knowledge.
  • Post-silicon validation and/or debugging experience.

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