ASIC DFT DV Technical Leader

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Nov 13, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $227k
$141k $281k
below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $177,250–$227,500 — the blue band above. At the midpoint, this role pays about $227k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT DV Technical Leader

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The ASIC DFT DV Technical Leader joins the Silicon One development organization to support the creation of hardware platforms for switching, routing, and wireless products. In this role, you will lead test planning and develop test benches to verify Design-for-Test architecture, ensuring support for ATE screening, in-system test, debug, and diagnostics. You will collaborate with front-end RTL and backend physical design teams to integrate and validate test logic across all implementation phases. Key responsibilities include driving reusable test and debug methodologies for new silicon device models, including bare die and stacked die. Required technical skills include System Verilog for testbench development, DVE/Verdi for debugging, and proficiency in TCL, Python, or Perl. Preferred expertise includes UVM, JTAG protocol, scan architecture, MBIST, and boundary scan.

Skills

System Verilog UVM DFT Python TCL Perl Verdi JTAG MBIST Scan Architecture Boundary Scan ATE RTL Physical Design post silicon validation

What you'll do

  • Develop test benches to verify Design-for-Test (DFT) architecture for ATE screening and in-system diagnostics.
  • Create comprehensive test plans based on complex design specifications for new silicon device models.
  • Integrate and validate test logic across all phases of implementation and post-silicon validation flows.
  • Drive reusable test and debug methodologies and standards for bare die and stacked die models.
  • Perform high-quality DFT verification by analyzing chip architecture with front-end RTL and backend physical design teams.
  • Debug hardware issues independently using tools such as DVE/Verdi.
  • Utilize System Verilog, TCL, Python, or Perl to develop and maintain test environments.

What we're looking for

  • Bachelor's degree plus 8 years of related experience, Master's plus 6 years, or PhD plus 3 years of related experience.
  • Prior experience in test planning based on complex design specifications.
  • Prior experience in testbench development using SystemVerilog.
  • Experience debugging using DVE/Verdi.
  • Experience with TCL, Python, or Perl.
  • UVM and advanced SystemVerilog knowledge (preferred).
  • Knowledge about JTAG protocol, scan architecture, MBIST, and boundary scan (preferred).

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