ASIC DFT Technical Leader

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$214,100–$309,800 / yr
Employment
Full-time
Posted
12 days ago
Freshness
Confirmed live yesterday
Closes
Nov 6, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $262k
$138k most similar roles pay here $328k

This role pays more than 90% of similar roles. Most pay $177,250–$230,400 — the shaded band above. At the midpoint, this role pays about $262k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 190 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 190 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader

Role Posting Log in to save

As an ASIC DFT Technical Leader within the Silicon One development organization, you will focus on Design-for-Test for next-generation networking chips. You will collaborate with front-end RTL and back-end physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. Your daily responsibilities include driving the DFT and quality process through implementation flows and post-silicon validation phases, including exposure to physical design signoff activities. The role requires expertise in Jtag protocols, Scan and BIST architectures, memory BIST, and boundary scan. You will utilize tools such as TestMax, Tetramax, Tessent, and PrimeTime while performing gate level simulation with VCS. Required skills include Verilog for custom DFT logic and IP integration, Test Static Timing Analysis, SystemVerilog Logic Equivalency checking, and validating test-timing of the design to solve complex hardware challenges.

Skills

Design-for-Test ASIC Verilog System Verilog JTAG Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis post silicon validation

What you'll do

  • Drive Design-for-Test (DFT) requirements early in the chip design cycle by collaborating with front-end and back-end teams.
  • Lead the DFT and quality processes through the entire implementation flow and post-silicon validation phases.
  • Manage physical design signoff activities for next-generation networking chips.
  • Develop custom DFT logic and integrate specialized IP into the hardware architecture.
  • Perform post-silicon debug from first silicon through production to ensure chip reliability.
  • Utilize EDA tools like TestMax, Tetramax, and Tessent to manage ATPG and scan architectures.
  • Conduct gate-level simulations and debug designs using VCS or other industry-standard simulators.
  • Validate test timing and perform logic equivalency checking using SystemVerilog.

What we're looking for

  • Bachelor's or Master's Degree in Electrical or Computer Engineering required.
  • At least 12 years of experience required.
  • Experience with post-silicon debug from first silicon to production is required.
  • Experience with Jtag protocols, Scan and BIST architectures (including memory BIST and boundary scan) is required.
  • Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime is required.
  • Experience with Gate level simulation and debugging with VCS or other simulators is required.
  • Verilog design experience for custom DFT logic and IP integration (preferred).
  • Familiarity with DFT CAD development, Static Timing Analysis, and System Verilog Logic Equivalency checking (preferred).

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