ASIC DFT Engineer

Cisco

Confirmed live today High trust
Closes in 3 days Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Employment
Full-time
Posted
15 days ago
Freshness
Confirmed live today
Closes
Oct 30, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $202k
$140k $259k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $177,250–$227,500.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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As an ASIC DFT Engineer within the Silicon One team, you will contribute to the development of next-generation networking chips. You will collaborate with front-end RTL and backend physical design teams to understand chip architecture and drive design-for-test requirements early in the design cycle. Your daily responsibilities include leading the DFT and quality process through the implementation flow and post-silicon validation phases, including physical design signoff activities. You will utilize technologies such as Jtag protocols, Scan and BIST architectures, memory BIST, and boundary scan. Required skills include experience with ATPG and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime, as well as gate level simulation using VCS. You will also perform post-silicon validation using ATE patterns and P1687.

Skills

DFT Verilog System Verilog ATPG JTAG Scan BIST VCS TestMax Tetramax Tessent PrimeTime Gate Level Simulation Post-Silicon Validation ATE P1687 Static Timing Analysis RTL EDA Tools

What you'll do

  • Drive DFT requirements early in the design cycle by working with front-end RTL and backend physical design teams.
  • Lead the DFT and quality process through the entire implementation flow and post-silicon validation phases.
  • Develop custom DFT logic and integrate IP using Verilog design experience.
  • Perform gate-level simulation and debugging using VCS and other simulators.
  • Execute post-silicon validation and debug using ATE patterns and P1687.
  • Conduct Test Static Timing Analysis and Logic Equivalency checking.
  • Manage Scan, BIST architectures, Jtag protocols, and ATPG using EDA tools like TestMax and Tessent.

What we're looking for

  • Bachelor's or Master's Degree in Electrical or Computer Engineering required with at least 3 years of experience.
  • Experience in innovative trends in DFT, test, and silicon engineering.
  • Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
  • Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • Experience with Gate level simulation and debugging using VCS and other simulators.
  • Post-silicon validation and debug experience with ATE patterns and P1687.
  • Verilog design experience for custom DFT logic and IP integration (preferred).
  • Test Static Timing Analysis and System Verilog Logic Equivalency checking (preferred).

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