Senior ASIC Timing Engineer, DFT

Nvidia

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Employment: Full-time
Posted: 77 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

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TL;DR · Senior ASIC Timing Engineer, DFT

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JOB TITLE: Senior ASIC Timing Engineer, DFT The Senior ASIC Timing Engineer, DFT joins a dynamic team to drive timing analysis and closure for DFT logic across all Nvidia chips, including GPUs, CPUs, DPUs, LPUs, and SoCs. This role involves managing timing closure at block, cluster, and full-chip levels while collaborating with PD, DFX, and Clocks teams to develop timing constraints for custom DFT designs. The engineer will drive timing and power convergence, implement ECOs, and improve workflows through automation and standardization. Required expertise includes Static Timing Analysis (STA) in advanced technology nodes, developing timing constraints, and using industry standard timing convergence tools. Preferred skills include experience with scan and iJTAG modes, domain specific STA for Serdes or Processors, and methodology development for complex hardware designs.

Skills

Static Timing Analysis STA DFT Timing Closure Timing Constraints DFT Logic Serdes iJTAG Scan PD DFX Clocks GPU

What you'll do

Drive timing analysis and closure for DFT logic on all Nvidia chips at block, cluster, and full-chip levels.
Develop timing constraints for custom DFT designs.
Collaborate with PD, DFX, and Clock teams to establish timing closure strategies.
Drive timing and power convergence across various chip architectures.
Implement Engineering Change Orders (ECOs) to fix timing paths.
Improve workflows and designs by introducing automation, resilience, and standardization.
Perform Static Timing Analysis (STA) on advanced technology nodes.

What we're looking for

BS in Electrical or Computer Engineering with 5+ years of experience or MS with 2+ years of experience.
Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
Expertise in analysis and fixing of timing paths through ECOs.
Expertise in developing timing constraints.
In-depth knowledge of industry standard timing convergence tools.
Understanding of DFT logic and experience with DFT timing closure for various modes like scan and iJTAG (preferred).
Background in domain specific STA and timing convergence such as Serdes, Processor, IO, or SMVA (preferred).
Experience in methodology and/or workflow development (preferred).

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