Sr. ASIC DFT Engineer (Silicon)

SpaceX

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$125,000–$150,000 / yr
Posted
today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $138k
$113k most similar roles pay here $237k

This role pays less than 91% of similar roles. Most pay $165,000–$216,250 — the shaded band above. At the midpoint, this role pays about $138k versus about $191k for comparable roles.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC DFT Engineer (Silicon)

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As a Sr. ASIC DFT Engineer in the Silicon Engineering team, you will be responsible for implementing and optimizing Design for Test (DFT) architectures using Siemens Tessent tools, integrating and verifying DFT IPs and fabrics within subsystems, setting up ATPG methodologies, and running gate-level simulations. You will also develop test scripts to automate processes and analyze data using languages like Perl, Python, Tcl, or C++. This role requires extensive experience in post-silicon bringup, silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs, along with hands-on experience with ATE platforms such as Teradyne and Advantest. You will collaborate closely with cross-functional teams to ensure DFT features meet production requirements and adhere to industry standards like IEEE 1500 and 1687.

Skills

Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 In-System_Test_(IST) boundary_scan_IEEE_1149_1 Automated_Test_Equipment_(ATE) Teradyne Advantest Streaming_Scan_Network cell-aware_fault_models_ATPG

What you'll do

  • Implement and optimize DFT architectures using Siemens Tessent tools.
  • Integrate and verify DFT IPs and fabrics within subsystems.
  • Set up and run ATPG tools for generating test patterns.
  • Run and debug non-timing gate-level simulations with SDF annotations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug.

What we're looking for

  • 5+ years of experience in semiconductor DFT engineering and post-silicon validation
  • Master’s or PhD in electrical, computer engineering, physics, or related field
  • Extensive hands-on experience with Automated Test Equipment (ATE) platforms for high-volume manufacturing test development
  • Experience collaborating across design, verification, and manufacturing teams to ensure DFT features meet production requirements
  • Knowledge of Siemens Tessent tools and industry standards for testability (e.g., IEEE 1500, 1687)
  • Hands-on experience with Streaming Scan Network and cell-aware fault models in ATPG
  • Excellent problem-solving skills and ability to work in a fast-paced environment

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