Senior ASIC DFT Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Irvine, CAAustin, TXPalo Alto
Salary
$165,000–$260,000 / yr
Posted
151 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k
This role $212k
$139k $273k
below market most similar roles pay here above market

This role pays more than 55% of similar roles. Most pay $177,250–$227,300 — the blue band above. At the midpoint, this role pays about $212k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Senior ASIC DFT Engineer

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The Sr. ASIC DFT Engineer joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructures. Working with cross-disciplinary teams, the engineer implements and optimizes DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST. Key responsibilities involve integrating DFT IPs, running ATPG tools for stuck-at and transition fault models, and performing gate-level simulations. The role requires creating and validating patterns for post-silicon bringup and ATE debug across silicon characterization cycles. Candidates must utilize Siemens Tessent tools and programming languages like Perl, Python, Tcl, or C++. The work addresses the technical challenge of enabling reliable connectivity through the Starlink network by developing high-performance chips for complex SoCs and advanced technology nodes such as 7nm and below.

Skills

ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ Post-Silicon Validation ATE Teradyne Advantest SDF IEEE 1500 IEEE 1149.1 Scan Insertion BIST

What you'll do

  • Implement and optimize DFT architectures including scan insertion, compression, and memory BIST using Siemens Tessent tools.
  • Integrate and verify DFT IPs and fabrics within various subsystems.
  • Set up and run ATPG tools to generate patterns for stuck-at, transition, and path delay fault models.
  • Run and debug non-timing and SDF annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug throughout silicon characterization.
  • Develop test scripts and automate processes using Perl, Python, Tcl, or C++.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
  • Master’s or PhD in electrical engineering, computer engineering, physics, or a related engineering field (preferred).
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs (preferred).
  • Hands-on experience with Automated Test Equipment (ATE) platforms like Teradyne or Advantest for high-volume manufacturing (preferred).
  • Experience with Siemens Tessent tools, including Streaming Scan Network and low-power DFT techniques (preferred).
  • Proficiency in programming languages such as Perl, Python, Tcl, or C++ to develop test scripts and automate processes.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for required Department of State authorizations.

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