Senior ASIC DFT Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$165,000–$260,000 / yr
Posted
105 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $212k
$142k most similar roles pay here $273k

This role pays more than 62% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $212k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior ASIC DFT Engineer

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Sr. ASIC DFT Engineer (Silicon) joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructure. This role involves implementing and optimizing DFT architectures, including scan insertion, compression logic, memory BIST, and logic BIST using Siemens Tessent tools. The engineer will integrate and verify DFT IPs within subsystems, run ATPG tools for various fault models, and perform gate-level simulations. Additionally, the position requires creating and validating patterns for post-silicon bringup and ATE debug across all cycles of silicon characterization. Key technical requirements include proficiency in Perl, Python, Tcl, or C++ to automate processes and analyze data. The role addresses the challenge of providing reliable connectivity through advanced hardware components designed for complex environments. Candidates should possess expertise in high-volume manufacturing test development, yield optimization, and low-power DFT techniques on advanced technology nodes.

Skills

DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation

What you'll do

  • Implement and optimize DFT architectures including scan insertion, compression logic, and memory BIST using Siemens Tessent tools.
  • Integrate and verify Design for Test (DFT) IPs and fabrics within various subsystems.
  • Run and manage Automatic Test Pattern Generation (ATPG) for stuck-at, transition, and path delay fault models.
  • Execute and debug non-timing and SDF annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug during silicon characterization.
  • Develop test scripts and automate processes using programming languages like Perl, Python, Tcl, or C++.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
  • Experience with Siemens Tessent tools for DFT architectures, including scan insertion, compression, and BIST.
  • Proficiency in developing test scripts and automating processes using Perl, Python, Tcl, or C++.
  • Experience with Automated Test Equipment (ATE) platforms like Teradyne or Advantest for high-volume manufacturing.
  • Knowledge of industry standards such as IEEE 1500, 1687, and 1149.1.
  • Ability to work extended hours and weekends to meet critical milestones.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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