Sr. ASIC DFT Engineer (Silicon)
SpaceX
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This listing doesn't post a salary. Most similar roles pay $164,900–$216,250.
Based on 240 similar postings.
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SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.
SpaceX currently has 604 open roles on FindRole.
Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.
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The Senior ASIC DFT Engineer role is part of the Silicon Engineering team and requires a highly experienced professional to implement and optimize Design for Test (DFT) architectures using Siemens Tessent tools. Responsibilities include integrating and verifying DFT IPs, setting up ATPG methodologies, running gate-level simulations, and creating post-silicon validation patterns. The ideal candidate will have hands-on experience with ATE platforms like Teradyne or Advantest, knowledge of IEEE standards for testability, and expertise in low-power DFT techniques. Strong collaboration skills are essential to work closely with design, verification, and manufacturing teams on complex SoCs at advanced technology nodes such as 7nm and below.
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