Sr. ASIC DFT Engineer (Silicon)

SpaceX

Quick summary

Work type
On-site
Location
Austin, TX
Posted
today

Market check

Salary context

How this pay compares to similar roles

Similar $191k
$152k most similar roles pay here $233k

This listing doesn't post a salary. Most similar roles pay $164,900–$216,250.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Sr. ASIC DFT Engineer (Silicon)

The Senior ASIC DFT Engineer role is part of the Silicon Engineering team and requires a highly experienced professional to implement and optimize Design for Test (DFT) architectures using Siemens Tessent tools. Responsibilities include integrating and verifying DFT IPs, setting up ATPG methodologies, running gate-level simulations, and creating post-silicon validation patterns. The ideal candidate will have hands-on experience with ATE platforms like Teradyne or Advantest, knowledge of IEEE standards for testability, and expertise in low-power DFT techniques. Strong collaboration skills are essential to work closely with design, verification, and manufacturing teams on complex SoCs at advanced technology nodes such as 7nm and below.

What you'll do

  • Implement and optimize DFT architectures using Siemens Tessent tools.
  • Integrate and verify DFT IPs and fabrics within subsystems.
  • Set up and run ATPG tools for generating test patterns.
  • Run and debug non-timing gate-level simulations with SDF annotations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug.

What we're looking for

  • 5+ years of experience in semiconductor DFT engineering and post-silicon validation.
  • Master’s or PhD in electrical engineering, computer engineering, physics, or related field.
  • Extensive hands-on experience with Siemens Tessent tools for DFT implementation and ATPG.
  • Experience with Automated Test Equipment (ATE) platforms like Teradyne and Advantest.
  • Strong problem-solving skills and ability to work in a fast-paced environment.

More like this

Similar roles

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Irvine, CA today $125,000$150,000
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 In-System_Test_(IST) boundary_scan_IEEE_1149_1 Automated_Test_Equipment_(ATE) Teradyne Advantest Streaming_Scan_Network cell-aware_fault_models_ATPG

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Sunnyvale, CA today $135,000$160,000
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 Teradyne Advantest Streaming_Scan_Network ATPG SDF_annotated_gate_level_simulations In-System_Test boundary_scan functional_testing board_level_diagnostics

ASIC Engineering Technical Leader- DFT

Cisco

Remote (San Jose, CA) 84 days ago $210,600$305,100
Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis Post-silicon validation
Remote

ASIC Engineering Technical Leader - DFT

Cisco

Remote (San Jose, CA) 63 days ago $183,800$263,600
Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis
Remote

Principal DFT Engineer (Silicon Engineering)

SpaceX

Irvine, CA today $200,000$285,000
Siemens_Tessent Perl Python Tcl C++ Verilog SystemVerilog UPF DRC ATE_testers ASIC_design RTL_simulation Gate_level_simulation SDF_annotated_simulations Design_for_Test(DFT) Scan_insertion ATPG_tools Pattern_compression Hierarchical_test_flows