Senior ASIC DFT Engineer

SpaceX

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Work type
On-site
Location
Austin, TXIrvine, CAPalo Alto
Posted
151 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

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At a glance

TL;DR · Senior ASIC DFT Engineer

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The Sr. ASIC DFT Engineer joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructures. Working with cross-disciplinary teams, the engineer implements and optimizes DFT architectures, including scan insertion, memory BIST, and logic BIST. Key responsibilities involve integrating DFT IPs, running Automatic Test Pattern Generation for stuck-at and path delay models, and performing gate-level simulations. The role requires creating patterns for post-silicon bringup and ATE debug while automating processes using Perl, Python, Tcl, or C++. Candidates must utilize Siemens Tessent tools and possess expertise in low-power DFT, IEEE 1500, and 1687 standards. This position solves critical connectivity challenges by ensuring the reliability and performance of hardware components within the Starlink satellite constellation and global ground networks.

Skills

ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ ATE Post-Silicon Validation Gate-Level Simulation SDF IEEE 1500 IEEE 1149.1 BIST Scan Insertion Failure Analysis

What you'll do

  • Implement and optimize DFT architectures including scan insertion, compression, and memory/logic BIST using Siemens Tessent tools.
  • Integrate and verify DFT IPs and fabrics within various subsystems.
  • Set up and run ATPG tools to generate patterns for stuck-at, transition, and path delay fault models.
  • Run and debug non-timing and SDF annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug through silicon characterization.
  • Develop test scripts and automate processes using Perl, Python, Tcl, or C++.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
  • Master’s or PhD in electrical engineering, computer engineering, physics, or a related engineering field (preferred).
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs (preferred).
  • Hands-on experience with Automated Test Equipment (ATE) platforms like Teradyne or Advantest for high-volume manufacturing (preferred).
  • Experience with Siemens Tessent workflows, including Streaming Scan Network and low-power DFT techniques (preferred).
  • Experience with In-System Test (IST), boundary scan (IEEE 1149.1), or functional testing in embedded systems (preferred).
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for required Department of State authorizations.

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