Senior ASIC DFT Engineer

SpaceX

Confirmed live yesterday Low trust

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Work type
On-site
Location
Austin, TX
Posted
105 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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TL;DR · Senior ASIC DFT Engineer

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As a Sr. ASIC DFT Engineer (Silicon), you will join a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. You will be responsible for implementing and optimizing DFT architectures, including scan insertion, compression logic, memory BIST, and logic BIST using Siemens Tessent tools. Your daily work involves integrating and verifying DFT IPs, running ATPG tools for stuck-at and path delay fault models, and performing gate-level simulations. You will create and validate patterns for post-silicon bringup and ATE debug while automating processes using Perl, Python, Tcl, or C++. The role focuses on solving complex connectivity challenges by ensuring high-performance silicon meets production requirements through advanced testability standards like IEEE 1500 and 1687. You will manage the full lifecycle of silicon characterization for sophisticated SoCs at advanced technology nodes.

Skills

DFT Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST Python Perl Tcl C++ ATE Teradyne Advantest SDF IEEE 1500 IEEE 1149.1 Boundary Scan Post-Silicon Validation

What you'll do

  • Implement and optimize DFT architectures including scan insertion, compression, memory BIST, and logic BIST using Siemens Tessent tools.
  • Integrate and verify Design for Test (DFT) IPs and fabrics within various subsystems.
  • Run and manage Automatic Test Pattern Generation (ATPG) for stuck-at, transition, and path delay fault models.
  • Execute and debug non-timing and SDF annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and ATE debug during silicon characterization.
  • Develop test scripts and automate processes using programming languages like Perl, Python, Tcl, or C++.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
  • Experience with Siemens Tessent tools for DFT architectures, including scan insertion, compression, and BIST.
  • Proficiency in running ATPG tools for stuck-at, transition, and path delay fault models.
  • Ability to develop test scripts and automate processes using Perl, Python, Tcl, or C++.
  • Experience with Automated Test Equipment (ATE) platforms like Teradyne or Advantest.
  • Knowledge of industry standards such as IEEE 1500, 1687, and 1149.1.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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