Senior ASIC DFT DV Engineer

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Nov 13, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k
This role $206k
$139k $257k
below market most similar roles pay here above market

This role pays more than 59% of similar roles. Most pay $177,250–$217,500 — the blue band above. At the midpoint, this role pays about $206k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Senior ASIC DFT DV Engineer

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The Senior ASIC DFT DV Engineer joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. This role involves thorough test planning and developing test benches to verify Design-for-Test architecture, supporting ATE screening, in-system test, debug, and diagnostics. The engineer will own the MBIST methodology across the Silicon One portfolio, creating reusable, hierarchical infrastructures for massive designs. Key responsibilities include collaborating with front-end RTL and backend physical design teams to drive high-quality DFT verification. Required skills include experience with memory architectures like SRAM and DRAM, debugging using DVE/Verdi, and proficiency in TCL, Python, or Perl. Preferred qualifications include Verilog/SV, experience with Automatic Test Equipment, and familiarity with industry-standard tools such as Synopsys DesignWare, SMS, TestMax, and Mentor Graphics Tessent.

Skills

DFT MBIST ATE Verilog Python TCL Perl DVE Verdi SRAM DRAM Synopsys DesignWare SMS TestMax Mentor Graphics Tessent

What you'll do

  • Develop test plans and test benches to verify Design-for-Test (DFT) architecture.
  • Own the MBIST methodology across the Silicon One portfolio to ensure high-quality memory testing.
  • Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market.
  • Coordinate with Front-end RTL and backend physical design teams to drive high-quality DFT verification.
  • Analyze chip architecture to support ATE screening, in-system test, debug, and diagnostics needs.
  • Address memory failure correlation in production environments.

What we're looking for

  • Bachelor’s in Electrical Engineering or equivalent with at least 7+ years of experience.
  • Master's degree with at least 4+ years of experience.
  • Prior experience in test planning based on complex design specification.
  • Experience debugging using DVE/Verdi.
  • Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.
  • Experience with TCL, Python or Perl.
  • Experience in Verilog/SV (preferred).
  • Experience addressing memory failure correlation in production (preferred).
  • Experience in silicon testing and Automatic Test Equipment (ATE) (preferred).
  • Experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent) (preferred).

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