ASIC DFT Technical Leader, MBIST

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TX
Salary
$214,100–$309,800 / yr
Employment
Full-time
Posted
54 days ago
Freshness
Confirmed live today
Closes
Nov 6, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $262k
$136k $328k
below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $177,250–$227,500 — the blue band above. At the midpoint, this role pays about $262k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader, MBIST

Role Posting Log in to save

ASIC DFT Technical Leader- MBIST will join the Silicon One development organization within the Common Hardware Group to craft next-generation networking chips. The role involves leading the MBIST methodology for silicon one chips, which includes designing and implementing robust, reusable MBIST architectures that are agnostic to specific tools and technologies. Key responsibilities include defining MBIST requirements for advanced technology nodes and packages while focusing on silicon quality and yield improvement. The successful candidate will utilize industry-standard DFT tools such as Synopsys DesignWare, SMS, TestMax, and Mentor Graphics Tessent. Required technical skills include experience with memory architectures like SRAM and DRAM, failure modes, and scripting in Python, TCL, or Perl. Preferred qualifications include proficiency in Verilog and System Verilog to address memory failure correlation in production.

Skills

ASIC DFT MBIST Python TCL Perl Verilog System Verilog Synopsys DesignWare SMS TestMax Mentor Graphics Tessent SRAM DRAM

What you'll do

  • Lead the MBIST methodology for Silicon One networking chips.
  • Design and implement robust, reusable MBIST architectures.
  • Specify MBIST architecture and implementation independent of specific tools or technologies.
  • Define MBIST requirements for advanced technology nodes and packages.
  • Plan and execute complex test strategies to improve silicon quality and yield.
  • Automate test generation and analysis using Python, TCL, or Perl scripts.
  • Address memory failure correlation in production environments.

What we're looking for

  • Bachelor's in Electrical Engineering with at least 12 years of experience in ASIC DFT.
  • Master's degree with at least 10 years of experience in ASIC DFT.
  • Experience with memory architectures such as SRAM and DRAM and their associated failure modes.
  • Experience with industry-standard DFT tools like Synopsys DesignWare, SMS, TestMax, or Mentor Graphics Tessent.
  • Scripting skills in Python, TCL, or Perl for test generation and analysis automation.
  • Ability to plan and execute complex test strategies with a focus on silicon quality and yield improvement.
  • Excellent communication skills for cross-team collaboration.
  • Experience in Verilog/System Verilog (preferred).
  • Experience addressing Memory failure correlation in production (preferred).

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