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Physical Design Floorplanning Synthesis Placement Routing Clock Tree Synthesis Static Timing Analysis Physical Verification Formal Equivalence Power Optimization IR-drop Electromigration EDA Tools Low Power Verification +9 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC Circuit Design +5 more Show less

ASIC RTL to GDS Flow Virtuoso Circuit Design Synthesis Place and Route System Simulation Design Verification Scripting +4 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

ASIC RTL to GDS Flow Virtuoso Synthesis Place and Route System Simulation Scripting Verification IC Package Logic Design +5 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation +4 more Show less

Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design +8 more Show less

Physical Design Synthesis PnR STA CTS Floorplanning Routing UPF Python Tcl Innovus ICC2 Fusion Compiler Genus PrimeTime Tempus LEC VLSI +13 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV +12 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation SoC +5 more Show less

Machine Learning Deep Learning Python C++ PyTorch TensorFlow EDA Tools RTL Synthesis Place and Route Clock Tree Synthesis Bayesian Optimization Active Learning LangGraph CrewAI Generative AI PDK Generation DRC LVS +13 more Show less

ASIC Physical Design Synthesis STA P&R DFT UPF CMOS floor planning Timing Closure IR Drop Analysis Physical Verification ECO AI Flow +9 more Show less

ASIC Physical Design Synthesis STA P&R Floor Planning Timing Closure IR Drop Analysis DFT UPF CMOS Mixed signal AI Flow RTL +9 more Show less

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

ASIC Physical Layout 3D IC DRC LVS TCL Python High-Speed Signal Interconnects SI PI RDL Advanced Packaging PCB Layout +8 more Show less

ASIC Physical Layout 3D IC DRC LVS TCL Python SI PI RDL Advanced Packaging PCB +7 more Show less

ASIC SoC RTL GDSII Synthesis Floorplanning Clock Tree Synthesis STA SDC UPF CPF DRC LVS Tcl Python Perl FinFET NoC AI/ML +14 more Show less

ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime +14 more Show less

Physical Design ASIC SoC Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python TCL Perl C/C++ Shell Scripting Linux Unix Clock Tree Synthesis Static Timing Analysis RC Extraction DFT Signal Integrity Floorplanning Routing +15 more Show less