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About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
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NVIDIA 2027 Internships: Hardware Physical Design / VLSI is a full-time internship role within the Hardware team where students will work on projects with measurable business impact. The role involves tasks related to floorplanning, place and route, static timing analysis, power integrity, IR drop analysis, physical verification, clock tree synthesis, and chip assembly. Candidates must possess knowledge in computer architecture, digital design, logic design, and CAD methodologies. The position requires familiarity with EDA vendor tool suites including ICC2, PrimeTime, dc_shell, Innovus, and SeaHawk. Additionally, the role may require programming skills in Perl, C, C++, TCL, Linux, Scheme, Python, SKILL, or Make. This position focuses on solving complex challenges within the domain of accelerated computing to support technologies such as AI and digital twins across various industries including gaming, robotics, and healthcare.
Perform floorplanning and physical design for VLSI circuits.
Execute Place and Route (P&R) processes to optimize chip layouts.
Conduct Static Timing Analysis (STA) to ensure timing closure.
Perform Power Integrity and IR Drop analysis on integrated circuits.
Complete Physical Verification tasks including DRC and LVS checks.
Implement Clock Tree Synthesis (CTS) for power and clock distribution.
Develop CAD and physical design methodologies using EDA tool suites.
Utilize scripting languages like Python, TCL, or Perl to automate design flows.
What we're looking for
Must be actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
Resume must clearly indicate the anticipated graduation date (month and year).
Experience or coursework in areas such as Floorplanning, Place and Route, Static Timing Analysis, Power Integrity, Physical Verification, or Clock Tree Synthesis.
Knowledge of Computer Architecture, Digital/Micro Electronics, Mixed-Signal Design, Logic Design, or CAD and Physical Design Methodologies.
Familiarity with circuit design, chip floor plans, timing closure, power and noise analysis, and back-end verification.
Experience with EDA tool suites such as Synopsys (ICC2, PrimeTime, dc_shell), Cadence (Innovus, Virtuoso), or Mentor tools.
Proficiency in programming languages and technologies including Perl, C, C++, TCL, Linux, Scheme, Python, SKILL, or Make.
SystemVerilog
UVM
Verilog
VHDL
Python
C++
C
TCL
Perl
Linux
VLSI Design
Digital Design
Formal Verification
Assertion-Based Verification
Verdi
DVE
Questa
JasperGold
Cadence Jasper
Simulation Tools