Senior Physical Design and Timing Engineer

Nvidia

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Quick summary

Work type: On-site
Location: Westford, MA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 7 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $216k

$136k $278k

below market most similar roles pay here above market

This role pays more than 80% of similar roles. Most pay $172,000–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Physical Design and Timing Engineer

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The Senior Physical Design and Timing Engineer joins the Networking Silicon engineering team to develop high-speed communication devices. This role involves driving physical design and timing for high-frequency, low-power DPUs and SoCs at the block, chiplet, and full-chip levels. Key responsibilities include analyzing design constraints, optimizing synthesis parameters for performance, power, and area targets, and managing frontend and backend implementation from RTL to gds2. The engineer will perform Static Timing Analysis, timing constraints management, and timing convergence, while utilizing ECOs to fix timing paths, crosstalk, and noise. Required skills include expertise in Synopsys PrimeTime or Cadence Tempus, logic synthesis, and logical equivalence checking. Candidates must also be proficient in Python, Tcl, and Make for automation and scripting tasks within the networking silicon domain.

Skills

Static Timing Analysis (STA) Synthesis ECO Physical Design RTL Python Tcl Make Synopsys PrimeTime Cadence Tempus Logical Equivalence Checking (LEC) DFT Floor-planning Routing Noise Analysis

What you'll do

Drive physical design and timing for high-frequency, low-power DPUs and SoCs at block, chiplet, and full chip levels.
Analyze and optimize design constraints and synthesis parameters to meet performance, power, and area targets.
Manage frontend and backend implementation from RTL to gds2, including synthesis and equivalence checking.
Perform floor-planning, timing constraint management, and timing and power convergence.
Implement ECOs to fix timing paths, crosstalk, and noise issues.
Execute physical design optimizations including placement, routing, cell sizing, buffering, and logic restructuring.
Develop automation and scripting tasks using Python, Tcl, and Make.
Perform Static Timing Analysis (STA) and manage timing convergence for various operating modes.

What we're looking for

Bachelor's degree in Electrical or Computer Engineering with 8 years of experience in Synthesis and Timing.
Master's degree with 4+ years of experience in Synthesis and Timing.
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints management, and timing convergence.
Expertise in fixing timing paths through ECOs, including crosstalk and noise analysis.
Expertise in physical design and optimization including placement, routing, cell sizing, buffering, and logic restructuring.
Background in logic synthesis and/or logical equivalence checking (LEC).
In-depth knowledge of industry standard EDA tools such as Synopsys PrimeTime or Cadence Tempus.
Proficiency in Python, Tcl, and Make for automation and scripting tasks.

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