Senior Physical Design and Timing Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Westford, MADurham, NC
Salary: $168,000–$264,500 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $216k

$130k most similar roles pay here $279k

This role pays more than 81% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Physical Design and Timing Engineer

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The Senior Physical Design and Timing Engineer joins the Networking Silicon engineering team to develop high-speed communication devices. This role involves driving physical design and timing for high-frequency, low-power DPUs and SoCs at the block, chiplet, and full-chip levels. The engineer will manage the flow from RTL to gds2, including synthesis, floor-planning, timing constraints, power convergence, and ECO implementation. Key responsibilities include performing Static Timing Analysis (STA), managing timing constraints, and addressing crosstalk and noise through logic restructuring, cell sizing, and buffering. Required technical skills include proficiency in Synopsys PrimeTime or Cadence Tempus, along with Python, Tcl, and Make for automation. The role focuses on solving complex hardware challenges within the networking silicon domain, specifically targeting high throughput and low latency requirements for advanced integrated circuits.

Skills

Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design

What you'll do

Drive physical design and timing for high-frequency, low-power DPUs and SoCs at block, chiplet, and full-chip levels.
Analyze and optimize design constraints and synthesis parameters to meet performance, power, and area targets.
Manage the implementation flow from RTL to GDS2, including synthesis, floor-planning, and timing constraints.
Perform Static Timing Analysis (STA) and manage timing constraints for full-chip or sub-chip designs.
Fix timing paths through Engineering Change Orders (ECOs), including crosstalk and noise analysis.
Execute physical design optimizations such as placement, routing, cell sizing, buffering, and logic restructuring.
Develop automation scripts and tools using Python, Tcl, and Make to streamline workflows.

What we're looking for

A Bachelor of Science in Electrical or Computer Engineering is required.
Candidates must have 8 years of experience in Synthesis and Timing with a BS degree.
Candidates must have at least 4 years of experience in Synthesis and Timing with an MS degree.
Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints management, and timing convergence is required.
Expertise in physical design optimization including placement, routing, cell sizing, buffering, and logic restructuring is required.
Proficiency in industry standard EDA tools such as Synopsys PrimeTime or Cadence Tempus is required.
Proficiency in Python, Tcl, and Make for automation and scripting tasks is required.
Experience in logic synthesis and/or logical equivalence checking (LEC) is required.