SoC Physical Design Engineer, PnR

Apple Inc

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$129,300–$225,300 / yr
Posted
5 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k
This role $177k
$113k $281k
below market most similar roles pay here above market

This role pays less than 72% of similar roles. Most pay $177,250–$233,850 — the blue band above. At the midpoint, this role pays about $177k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, PnR

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JOB TITLE: SoC Physical Design Engineer, PnR The SoC Physical Design Engineer, PnR will join the hardware team to manage the physical implementation of design partitions from netlist to tapeout for a highly complex SOC using innovative process technology. This role involves collaborating with architecture, CAD, timing, and logic design teams to drive physical aspects early in the design cycle. Key responsibilities include completing netlist to GDS2 implementation, performing timing, physical, and electrical verification, and driving signoff closure. The candidate must possess knowledge of chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route, power grid, timing, and physical design verification. Required skills include understanding logic gates and experience with Verilog, VHDL, Python, Perl, TCL, and SPICE to resolve design and flow issues.

Skills

PnR Physical Design VLSI STA DRC LVS EMIR Redhawk Totem Voltus Verilog VHDL Python Perl TCL SPICE GDS2 Floor-planning Physical Synthesis

What you'll do

  • Drive physical design aspects early in the design cycle by collaborating with the logic design team.
  • Complete the full netlist to GDS2 implementation for specific design partitions.
  • Perform timing, physical, and electrical verification to achieve signoff closure.
  • Resolve and improve design and flow issues related to physical design.
  • Identify potential solutions for technical bottlenecks and drive execution.
  • Manage floor-planning, place and route, and power grid design for complex SOCs.

What we're looking for

  • Minimum BS degree.
  • Basic understanding of logic gates.
  • Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), and EMIR (Redhawk/Totem/Voltus).
  • Previous internship, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design (preferred).
  • Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields (preferred).
  • Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE (preferred).

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