Senior Staff Engineer, Physical Design

Samsung Electronics

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$180,200–$270,400 / yr
Employment
Full-time
Posted
10 days ago
Freshness
Confirmed live yesterday
Closes
Nov 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $225k
$136k most similar roles pay here $285k

This role pays more than 72% of similar roles. Most pay $170,950–$233,050 — the shaded band above. At the midpoint, this role pays about $225k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 84 open roles on FindRole.

Listed pay typically runs $106,000–$200,250 across 78 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Senior Staff Engineer, Physical Design

Role Posting Log in to save

Senior Staff Engineer, Physical Design joins the Advanced Design Technology and Design Implementation team to shape physical implementation and methodology innovation for high-performance GPU and system-level IP. This role involves managing critical stages of the physical design flow, including synthesis, floorplanning, placement, routing, clock tree synthesis, timing closure, and signoff across advanced-node designs. The engineer will drive power, performance, and area goals while developing automation, tool optimization, and scalable design practices to improve implementation quality. Key technical requirements include proficiency in industry-standard EDA tools such as Synopsys or Cadence suites, including ICC2, Fusion Compiler, Innovus, PrimeTime, Tempus, and StarRC. Candidates must possess strong scripting skills in Python, Tcl, Shell, or Perl. The role addresses complex implementation challenges for advanced-node GPU and SoC designs to ensure silicon readiness and high-quality performance across various market segments.

Skills

Physical Design GPU SoC Synthesis Floorplanning Placement Routing Clock Tree Synthesis Timing Closure STA Signoff DRC LVS Python Tcl Shell Perl Synopsys Cadence ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC

What you'll do

  • Execute full physical design flows including synthesis, floorplanning, placement, routing, and timing closure for GPU and SoC designs.
  • Optimize power, performance, and area (PPA) targets through advanced implementation strategies and congestion management.
  • Drive methodology innovation by developing automation, tool optimizations, and scalable design practices to improve production quality.
  • Resolve complex technical challenges related to signal integrity, reliability, and advanced-node physical verification.
  • Collaborate with cross-functional teams to adapt physical design flows for cutting-edge semiconductor nodes.
  • Mentor junior engineers and foster a culture of ownership and continuous learning within the team.

What we're looking for

  • Bachelor's degree in Computer Science or Engineering with 11+ years of experience, Master's with 9+ years, or Ph.D. with 7+ years.
  • At least 7 years of hands-on experience with full physical design implementation flows including synthesis, P&R, CTS, timing closure, and signoff.
  • Strong expertise in physical design for complex GPU or SoC designs, including low-power design, physical verification, and advanced-node challenges.
  • Strong experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations.
  • Proficiency with industry-standard EDA tools such as Synopsys (ICC2/Fusion Compiler, PrimeTime, StarRC) or Cadence (Innovus, Tempus).
  • Strong scripting and automation skills in Python, Tcl, Shell, or Perl.
  • Experience leading technical initiatives, driving methodology innovation, and mentoring engineers.
  • Export Control This role may require access to information subject to U.S. export control laws.

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