Senior Physical Design Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$141,760–$212,640 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Oct 23, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k
This role $177k
$129k $263k
below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $177,237–$227,500 — the blue band above. At the midpoint, this role pays about $177k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Physical Design Engineer

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The Sr Physical Design Engineer joins a team developing high-performance, multi-gigabit SerDes PHY and advanced IP designs. In this role, you will drive the physical implementation of high-performance RTL blocks through the full RTL-to-GDS lifecycle, including synthesis, floorplanning, timing-driven place and route, and final signoff. You will develop automated design flows for clock tree synthesis, power gating, and scan stitching while optimizing for timing, power, area, and electrical quality. The position requires proficiency in Verilog, industry EDA tools for static timing analysis, and physical verification. You will solve complex physical design challenges for high-speed datapath and control logic, focusing on improving design methodologies and automated flows to deliver complex IP efficiently for high-speed, low-power applications.

What does a Physical Design Engineer earn?

Median $177300 from 31 postings across 9 companies.

See salary data

Skills

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation

What you'll do

  • Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, place and route, and signoff.
  • Develop and apply automated design flows for clock tree synthesis, power gating, and buffer insertion.
  • Analyze and optimize designs to meet specific timing, power, area, and electrical quality targets.
  • Perform logic equivalence, timing, physical, and electrical quality checks.
  • Troubleshoot implementation and timing challenges in collaboration with design teams to drive issues to closure.
  • Identify opportunities to improve automation, design methodology, and overall design cycle time.
  • Support the final signoff and delivery of large, high-performance IP blocks.

What we're looking for

  • Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
  • Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, and scan stitching.
  • Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.
  • Perform and support logic equivalence, timing, physical, and electrical quality checks.
  • Experience taking digital designs through the RTL-to-GDS physical design flow (preferred).
  • Experience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs (preferred).
  • Experience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic (preferred).
  • Bachelor's or master’s degree in electrical engineering, Computer Science, or a related technical discipline (preferred).

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