Senior Physical Design Engineer

Nvidia

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Quick summary

Work type
On-site
Location
Westford, MA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
1 day ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $177k
$124k most similar roles pay here $247k

This role pays less than 61% of similar roles. Most pay $168,200–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1371 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Physical Design Engineer

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As a Senior Physical Design Engineer on the Networking Silicon engineering team, you will lead all aspects of physical design and implementation for SOC devices targeted at networking markets. Your daily responsibilities involve managing the full RTL2GDS flow, including trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification at both the partition and chiplet levels. You will also contribute to establishing methodologies and flow automation while applying ML/AI solutions. The role requires expertise in 5nm, 4nm, and 3nm technologies using Synopsys and Cadence EDA tools. Essential skills include RC extraction, IR drop analysis, and scripting in Python, Perl, Tcl, and Make. You will solve complex problems related to high-speed communication devices to deliver the highest throughput and lowest latency for networking hardware.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

See salary data

Skills

Physical Design VLSI RTL2GDS Timing Closure Power and Clock Distribution IR Drop Analysis RC Extraction Synopsys (ICC2 Cadence (Genus Python Perl Tcl Make

What you'll do

  • Lead all aspects of physical design and implementation for SoC devices in the networking market.
  • Execute full RTL2GDS physical chip development including synthesis, place and route, and timing closure.
  • Manage power and clock distribution, as well as power and noise analysis.
  • Perform physical verification and RC extraction/correlation for advanced nodes like 5nm, 4nm, and 3nm.
  • Develop and debug design flows using ML/AI solutions.
  • Create floorplans and manage chip assembly at the partition and chiplet levels.
  • Utilize industry-standard EDA tools from Synopsys and Cadence to deliver designs to production.

What we're looking for

  • BSEE / MSEE or equivalent experience.
  • 5 years of experience in VLSI physical design implementation on 5nm, 4nm, and 3nm technology.
  • A successful track record of delivering designs to production.
  • Ability to assist in design flow development and debugging, including the application of ML/AI solutions.
  • Proficiency as a power user of Synopsys (ICC2/DC/PT/STAR/ICV) and Cadence (Genus/Innovus/Tempus) tools.
  • Experience in timing closure, clock/power distribution, RC extraction, and tapeout solutions.
  • Strong analytical and debugging skills.
  • Proficiency using Python, Perl, Tcl, and Make scripting (preferred).

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