Senior Staff Engineer, Physical Design (Floorplanning)

Samsung Electronics

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$180,200–$270,400 / yr
Employment
Full-time
Posted
64 days ago
Freshness
Confirmed live yesterday
Closes
Oct 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $225k
$133k most similar roles pay here $285k

This role pays more than 78% of similar roles. Most pay $162,000–$220,500 — the shaded band above. At the midpoint, this role pays about $225k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 84 open roles on FindRole.

Listed pay typically runs $106,000–$200,250 across 78 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Senior Staff Engineer, Physical Design (Floorplanning)

Role Posting Log in to save

Senior Staff Engineer, Physical Design (Floorplanning) joins the Advanced Design Technology and Design Implementation team to shape physical implementation and methodology innovation for high-performance GPU and system-level IP. This role focuses on top-level floorplanning, power-grid implementation, and achieving market-differentiating power, performance, and area goals across advanced technology nodes. The engineer will manage placement, routing, timing closure, and signoff while developing automated physical design flows to improve scalability and reliability. Key technical requirements include expertise in synthesis, clock tree synthesis, and physical verification for complex SoC designs. Candidates must be proficient with industry-standard EDA tools such as FusionCompiler, Innovus, PrimeTime, or Tempus, alongside scripting skills in Python, Tcl, Shell, or Perl. The role addresses the challenge of delivering high-quality silicon for next-generation GPU products by solving complex implementation hurdles and optimizing advanced-node designs.

Skills

Physical Design Floorplanning Placement Routing Clock Tree Synthesis Timing Closure STA Power-grid Design DRC LVS Python Tcl Shell Perl FusionCompiler Innovus PrimeTime Tempus StarRC RedHawk

What you'll do

  • Execute top-level floorplanning and power-grid implementation for high-performance GPU and system-level IP.
  • Drive physical design flow innovations including automation, tool optimization, and scalable design practices.
  • Achieve market-differentiating PPA targets through power optimization, congestion management, and STA-driven convergence.
  • Resolve complex implementation challenges across advanced-node designs in collaboration with hardware and system teams.
  • Manage full-chip and block-level implementation including placement, routing, timing closure, and signoff.
  • Develop and rewrite physical design flows to improve implementation quality and productivity.
  • Provide technical guidance to block implementers and influence top-level floorplanning decisions.
  • Mentor junior engineers and foster a culture of ownership and continuous learning.

What we're looking for

  • Bachelor's degree in Computer Science or Engineering with 11+ years experience, Master's with 9+ years, or Ph.D. with 7+ years.
  • At least 7 years of hands-on experience with full physical design implementation flows including synthesis, P&R, CTS, timing closure, and signoff.
  • Expertise in top-level floorplanning for complex GPU/SoC designs, low-power design, physical verification (DRC/LVS), and advanced-node challenges.
  • Experience in power-grid design and implementation using tools like FusionCompiler or Innovus, and robustness analysis using RedHawk or equivalent.
  • Proficiency in industry-standard EDA tools including Synopsys or Cadence suites for P&R, timing analysis (PrimeTime/Tempus), and extraction (StarRC).
  • Strong scripting and automation skills in Python, Tcl, Shell, or Perl.
  • Experience leading technical initiatives, driving methodology innovation, and mentoring engineers.
  • Authorization to access information subject to U.S. export control laws.

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