Physical Design Technical Leader

What you'll do

• Lead end-to-end RTL-to-GDSII physical design implementation across advanced technology nodes.
• Drive hierarchical floorplanning and complex mixed-signal macro placement for optical transceivers and driver ICs.
• Perform signoff analysis including STA, IR/EM, and PV to ensure first-pass silicon success.
• Architect and scale digital implementation flows using custom TCL and Python automation.
• Manage physical execution across PnR, CTS, MMMC timing closure, and ECO iterations.
• Resolve complex cross-domain bottlenecks by coordinating with RTL, Analog, DFT, Packaging, and CAD teams.
• Debug and fix complex Electromigration, IR drop, RC parasitic extraction, and crosstalk violations.
• Optimize power grid design and perform functional equivalence checking for ECOs.

What we're looking for

• Bachelor's degree plus 8 years of related experience, Master's plus 6 years, or PhD plus 3 years of related experience.
• Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes.
• Prior hands-on experience with the full physical design flow at block and/or chip level.
• Prior hands-on expertise in EDA tool flows, back-end sign-off criteria, and workflow automation using Python, TCL, and Shell scripts.
• Prior experience in closing designs with high-speed, high-density, macro-dominant, and I/O cell–intensive blocks (preferred).
• Prior experience in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation (preferred).
• Prior experience in physical design fundamentals including EM, IR drop, RC parasitic extraction, and crosstalk/glitch violations (preferred).
• Prior hands-on experience with functional equivalence checking, functional ECOs, power grid design, and mixed-signal integration (preferred).