below marketmost similar roles pay hereabove market
This role pays more than
72%
of similar roles. Most pay
$174,600–$241,961
— the blue band above.
At the midpoint, this role pays about
$231k
versus about
$208k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
694 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 651 roles with salary data.
The Principal Physical Design Engineer joins the Compute Silicon & Manufacturing Engineering team within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering. This role focuses on the design, development, and manufacturing of state-of-the-art computer chips, specifically the Azure Cobalt. The engineer will lead and execute the end-to-end physical design flow, including synthesis, floorplanning, place-and-route, and clock construction. Key responsibilities involve managing RTL to GDS implementation, performing timing signoff, physical verification, EMIR, formal equivalence, and low-power verification. The candidate must utilize data-driven approaches to influence design tools and methodologies while collaborating with CAD, RTL, DFT, and Architecture teams. This position solves critical hardware manufacturing challenges to ensure high-quality, high-volume production of cloud infrastructure components while optimizing for power, performance, and area trade-offs.
What does a Physical Design Engineer earn?
Median $177300 from 31 postings across 9 companies.
Lead and execute the end-to-end physical design flow from synthesis through place-and-route for multiple designs.
Ensure completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Manage clock construction, clock tree synthesis (CTS), and related methodology exploration for SOC blocks.
Own the RTL to GDS implementation and technical ownership within the Physical Design domain.
Influence design tools, flows, and methodologies using a data-driven approach to optimize construction and signoff.
Partner with CAD and methodology teams to identify and resolve Physical Design Technology File (TFM) issues.
Provide technical leadership and clear communication on project status and planning to cross-functional teams.
What we're looking for
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of technical engineering experience.
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 10+ years of technical engineering experience.
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 12+ years of technical engineering experience.
Equivalent experience to the degree and years of experience requirements.
Ability to meet Microsoft, customer, and/or government security screening requirements.
Must provide proof of citizenship, US residency, or other protected status for export control regulations.
Track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification (preferred).
20+ years of experience in Physical Design (preferred).
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design
Colorado Springs, CO+160 days ago
$129,400–$207,000
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design
Colorado Springs, CO+129 days ago
$129,400–$207,000
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design