Senior Physical Design Methodology Engineer, Innovus Flows

Nvidia

Confirmed live today High trust

Remote

Quick summary

Work type: Remote
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 34 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k

This role $216k

$139k most similar roles pay here $278k

This role pays more than 68% of similar roles. Most pay $174,375–$231,950 — the shaded band above. At the midpoint, this role pays about $216k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1388 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1103 roles with salary data.

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At a glance

TL;DR · Senior Physical Design Methodology Engineer, Innovus Flows

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Senior Physical Design Methodology Engineer, Innovus Flows will join the physical design methodology team to drive innovation across various product lines including GPU, CPU, and Network processors. The role focuses on developing innovative methodologies for implementation on advanced technology nodes with a heavy emphasis on PPA improvements and runtime flow optimization. You will collaborate with cross-functional teams like RTL, synthesis, DFT, and foundry to improve tool performance and design turnaround times using AI/ML approaches. Key responsibilities include managing power distribution networks, thermal management, and timing closure. Required expertise includes STA, extraction, RC correlation, and low power design using UPF. Candidates must be proficient in the Cadence EDA tool suite, including Innovus, Genus, Tempus, and Quantus, alongside programming skills in TCL, Perl, Python, and C++. Experience with ML libraries like PyTorch or scikit-learn is highly valued.

Skills

Physical Design EDA Tools TCL Python C++ Perl Innovus Genus Tempus Quantus Joules STA UPF PyTorch NumPy SciPy scikit-learn RC Correlation

What you'll do

Develop innovative physical design methodologies for GPU, CPU, and SoC implementations on advanced technology nodes.
Optimize Power, Performance, and Area (PPA) metrics across all product lines including Datacenter AI and Networking.
Improve the runtime performance of physical design flows to meet accelerated chip cycle demands.
Collaborate with internal and external partners to drive improvements in EDA tools and methodologies.
Integrate AI/ML approaches into CAD workflows to improve design performance and designer productivity.
Execute complex timing, power optimization, and routing methodologies at place, cts, route, and postroute stages.
Perform EM and IR analysis while ensuring closure for high-performance and low-power designs.
Develop scripts using TCL, Perl, Python, or C++ to automate and enhance physical design flows.

What we're looking for

MS in Electrical or Computer Engineering (or equivalent experience).
Minimum 7 years of experience in Physical Design.
Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes.
Strong understanding of physical design optimization, routing methodologies, and STA, extraction, timing, and RC correlation.
Experience in low power design with UPF and use of FSDB/SAIFs for power optimization.
Solid understanding of EM and IR analysis, synthesis, hierarchical design, pinning, and budgeting flows.
Expertise in industry standard EDA tools and proficiency in TCL, Perl, Python, and C++.
Experience applying ML models, LLMs, or agentic AI to EDA/PD problems (preferred); Proficiency with Cadence EDA tool suite (preferred).

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