ML and AI Physical Design Methodology Engineer

Nvidia

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Work type: On-site
Location: Santa Clara, CAAustin, TXHillsboro, OR
Employment: Full-time
Posted: 14 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

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At a glance

TL;DR · ML and AI Physical Design Methodology Engineer

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JOB TITLE: ML and AI Physical Design Methodology Engineer The ML and AI Physical Design Methodology Engineer joins the Networking Silicon engineering team to develop high-speed communication devices with high throughput and low latency. This role involves architecting, integrating, and deploying AI/ML-driven solutions into production physical design flows to solve state-of-the-art problems and improve PPA. Key responsibilities include developing flow and tool methodologies for P&R, timing analysis, closure, IR/Signal-EM convergence, power and noise analysis, back-end verification, chip floorplan, and power and clock distribution. The engineer will utilize data-based analysis and algorithmic solutions for PPA checks. Required skills include an MS in Electrical, Computer Engineering, or Computer Science, plus five years of ML/AI solution development experience. Technical requirements include strong Python and Tcl programming skills and familiarity with ML frameworks.

Skills

Python Tcl ML Frameworks Physical Design P&R Timing Analysis IR/Signal-EM Power and Noise Analysis Back-end Verification Chip Floorplan Power and Clock Distribution PPA

What you'll do

Architect, integrate, and deploy AI/ML-driven solutions into production physical design flows.
Develop creative solutions to state-of-the-art physical design problems to improve PPA.
Formulate and develop ML-based solutions for physical design challenges.
Develop flow and tool methodologies for P&R, timing analysis, and closure.
Manage convergence in IR/Signal-EM, power and noise analysis, and back-end verification.
Oversee chip floorplan, power and clock distribution, and chip assembly.
Perform data-based analysis and algorithmic solutions for PPA checks and improvements.

What we're looking for

MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in ML/AI based solution development.
Strong Python and Tcl programming skills with familiarity in ML frameworks.
Proven experience in implementing ML-based solutions.
Experience with Physical Design workflows.
Ability to formulate, develop, and automate workflows.
Knowledge of P&R, timing analysis, IR/Signal-EM convergence, power/noise analysis, and back-end verification.
Knowledge of chip floorplan, power and clock distribution, and chip assembly.

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