Senior Staff Physical Design PPA Engineer

Samsung Electronics

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $180,200–$270,400 / yr
Employment: Full-time
Posted: 64 days ago
Freshness: Confirmed live yesterday
Closes: Oct 31, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $225k

$147k most similar roles pay here $284k

This role pays more than 71% of similar roles. Most pay $177,250–$233,050 — the shaded band above. At the midpoint, this role pays about $225k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 84 open roles on FindRole.

Listed pay typically runs $106,000–$200,250 across 78 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Senior Staff Physical Design PPA Engineer

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As a Sr. Staff Physical Design PPA Engineer, you will join the Design Implementation team to develop and innovate design recipes aimed at improving Power, Performance, and Area for premium IPs. You will lead PPA initiatives by identifying opportunities, tracking progress, and executing solutions that meet project requirements while driving flow and methodology improvements to automate Physical Design Implementation. Your daily work involves hands-on responsibility from synthesis to place and route in chip-level and hierarchical environments, including floor planning, power grid implementation, and area/congestion optimization. You will utilize TCL, Perl, Shell, and Python for scripting to solve design issues during block closure. The role focuses on the technical challenge of optimizing high-performance computing IP, specifically addressing complex semiconductor products like GPUs that require advanced signoff flows for timing, physical verification, and reliability in advanced process nodes.

Skills

Physical Design STA Synthesis floor planning Clock Tree Synthesis TCL Python Perl Shell ASIC SOC FinFET Signal Integrity DFM Power Grid

What you'll do

Develop and innovate design recipes to improve Power, Performance, and Area for premium IPs.
Lead PPA initiatives by identifying opportunities and executing solutions that meet project requirements.
Drive flow and methodology improvements to automate Physical Design Implementation processes.
Manage the full implementation cycle from synthesis through place and route to signoff flows.
Execute floor planning, power grid implementation, and area/congestion optimization in chip-level environments.
Resolve design issues related to block closure by collaborating with RTL and SoC teams.
Ensure all designs meet strict frequency, power, and area requirements during physical verification.

What we're looking for

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field with 10+ years of experience.
Master's degree with 8+ years of experience.
PhD with 6+ years of experience.
Solid understanding of the SOC/ASIC design flow with specific experience in taping out designs.
Experience with synthesis, block, and full chip implementation using current industry P&R/STA flows and tools.
Proficiency in scripting and programming using TCL, Perl, Shell, and/or Python.
Knowledge of Electrical Engineering fundamentals, analytical aptitude, and strong communication skills.
Export Control This role may require access to information subject to U.S. export control laws.

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