below marketmost similar roles pay hereabove market
This role pays less than
58%
of similar roles. Most pay
$169,175–$216,250
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$193k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
694 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 651 roles with salary data.
The Senior Physical Design Engineer joins the Compute Silicon & Manufacturing Engineering organization within the Cloud Hardware and Infrastructure Engineering team. This role focuses on the design, development, and manufacturing of Microsoft's computer chips, specifically the Azure Cobalt. The engineer will drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. Key responsibilities include clock construction, CTS, and methodology exploration to optimize SOC blocks. The candidate must utilize technical expertise in RTL to GDS implementation, data-driven flow optimization, and PPA trade-offs. Required skills include experience with floorplanning, extraction, and production silicon tape-outs in advanced foundry process nodes while collaborating with CAD, RTL, DFT, and Architecture teams.
What does a Physical Design Engineer earn?
Median $177300 from 31 postings across 9 companies.
Drive end-to-end execution from synthesis through place-and-route for large designs.
Complete all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Manage clock construction and Clock Tree Synthesis (CTS) for SOC blocks.
Execute RTL to GDS implementation within the Physical Design domain.
Influence design tools, flows, and methodologies using a data-driven approach.
Explore and optimize methodologies for clock construction and related SOC block improvements.
Partner with CAD and methodology teams to identify and resolve Physical Design TFM issues.
What we're looking for
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year(s) technical engineering experience.
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years technical engineering experience.
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years technical engineering experience.
Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
Must provide proof of citizenship, U.S. permanent residency, or other protected status for export-controlled information access.
Min 7+ years of experience in semiconductor design (preferred).
Proven track record in Physical Design implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification (preferred).
Production silicon tape-outs experience in advanced foundry process nodes (preferred).
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design
Colorado Springs, CO+160 days ago
$129,400–$207,000
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design
Colorado Springs, CO+129 days ago
$129,400–$207,000
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floor-planning
Layout
TCL
Perl
EDA Tools
IC Design