Physical Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CAColorado Springs, CO
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live today
Closes
Oct 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k
This role $187k
$130k $268k
below market most similar roles pay here above market

This role pays less than 58% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $187k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 241 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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The Physical Design Engineer will join the Data Center Solutions Group to support the development of next generation AI/ML ecosystems through PCIe Switch Products and Enterprise Storage Products. This role requires in-depth expertise in all physical design aspects of taking RTL to silicon tape-out. Key responsibilities include executing physical design, synthesis, physical verification, and timing closure setup. The engineer will perform top-level STA EM/IR analysis, place and route clock tree synthesis, floor-planning, and layout. The position involves collaborating with IC Design RTL Engineers and developing flow methodologies. Required technical skills include proficiency in TCL and PERL scripting for related EDA tools. Candidates must possess a Bachelor’s degree in Electrical Engineering or Electronics Engineering and have over twelve years of relevant experience in the full physical design cycle.

What does a Physical Design Engineer earn in California?

Median $184362 from 30 postings across 9 companies.

See salary data

Skills

Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools

What you'll do

  • Execute the full physical design cycle from RTL to silicon tape-out.
  • Perform synthesis, physical verification, and timing closure setup using various strategies.
  • Conduct top-level STA EM/IR analysis and Place and Route Clock Tree Synthesis.
  • Implement custom clock trees, insertion reduction, and skew balancing techniques.
  • Manage floor-planning and layout processes for complex IC designs.
  • Develop methodologies and flows for top-level floorplanning.
  • Write TCL and PERL scripts to automate and manage related EDA tools.

What we're looking for

  • Bachelor’s degree in Electrical Engineering or Electronics Engineering.
  • 12+ years of relevant experience.
  • In-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.
  • Proficiency in TCL and PERL scripting for related EDA tools.
  • Experience with Synthesis, Physical Verification, and Timing Closure Setup.
  • Experience with Floor-planning and Layout.
  • Excellent verbal and written communication skills.
  • In-depth experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis (preferred).

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