below marketmost similar roles pay hereabove market
This role pays more than
70%
of similar roles. Most pay
$165,825–$229,575
— the blue band above.
At the midpoint, this role pays about
$218k
versus about
$198k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The Physical Design Engineer joins the ASICS Engineering team to support the development of high-performance computing, AI, mobile, automotive, and data center semiconductor technologies. This role involves executing the full physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs. Key responsibilities include floorplanning, partitioning, power planning, IR-drop analysis, clock tree synthesis, routing, and timing closure across Multi-Mode Multi-Corner scenarios. The engineer will resolve signal integrity issues, perform RC extraction, and implement engineering change orders. Required technical skills include experience with Cadence Innovus, Synopsys Fusion Compiler, and Synopsys PrimeTime SI. Candidates must demonstrate proficiency in Python, Perl, TCL, Shell scripting, and C/C++ within Linux/Unix environments to develop automation tools and innovative low-power implementation methodologies.
What does a Physical Design Engineer earn?
Median $177300 from 31 postings across 9 companies.
Execute all stages of the physical design flow from synthesized netlist to tape-out.
Perform floorplanning, partitioning, power planning, and IR-drop analysis for complex ASICs and SoCs.
Execute placement, clock tree synthesis, routing, and timing optimization across MMMC scenarios.
Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
Perform RC extraction, physical verification, and formal verification activities.
Implement engineering change orders and support design convergence through sign-off.
Develop automation and productivity tools using scripting languages and software development techniques.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
10+ years of industry experience or relevant academic/project experience in Physical Design.
Experience in ASIC/SoC Physical Design implementation (preferred).
Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler (preferred).
Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI (preferred).
Programming and automation skills using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments (preferred).
ASIC Design
NoC
Physical Design
Python
TCL
Perl
C
Linux
Unix Shell
AMBA Protocol
Design Compiler
Fusion Compiler
Genus
Primetime
Prime power
Innovus
DFT
Formal Verification
Signal Integrity