Browse tech roles

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa Modelsim Formal Verification AXI PCIe DSP GitLab Constrained Random Testing Assertions Register Abstraction Layer Xilinx +14 more Show less

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa ModelSim Formal Verification AXI PCIe DSP GitLab VHDL Constrained Random Testing Assertions Register Abstraction Layer +14 more Show less

ASIC FPGA SystemVerilog Verilog UVM OVM SVA Digital Signal Processing Formal Verification Constrained Random Testing Functional Coverage Synthesis Place and Route Agile Microsoft Office +10 more Show less

Solidworks Ansys Icepack Ansys Mechanical Python Excel Allegro Thermal Management PCB Design Simulations Profilometry Keyence ATE Test Hardware Mechanical Prototyping +8 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification +9 more Show less

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification +9 more Show less

ASIC FPGA Verilog VHDL SystemVerilog Python Tcl Perl Vivado Libero ISE Synplify QuestaSim UVM OVM SVA Digital Design Synthesis Place and Route Timing Closure Clock-Domain-Crossing Logic Analyzer Oscilloscope +18 more Show less

VHDL ASIC Design FPGA Design FPGA-to-ASIC Conversion Vivado Libero Mentor Cadence Xilinx Microsemi JTAG Oscilloscope Logic Analyzer Synthesis Place and Route Power Utilization System Simulation +12 more Show less

ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation +12 more Show less

STA DFT RTL Design CDC RDC SDC Python TCL Perl Makefile Tessent PCIE BIST Scan Shift/Capture Conformal Verification +10 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

System Verilog UVM Python Verilog RTL VCS Verdi OOPS ASIC Verification Computer Architecture Functional Coverage Scripting +7 more Show less

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD SPICE PAM4 SerDes 2.5D Fanout HBM UCIe IBIS Vector Network Analysis Transmission Line Theory Electromagnetics +11 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation +12 more Show less

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT RTL Noise Analysis Placement Routing Equivalence Checking Scan BIST AMS GPU LPU +10 more Show less

Verilog RTL ASIC Design SOC Design Lint CDC RDC Synthesis ECO STA Physical Design Python Perl Tcl GenAI System Architecture +11 more Show less

Verilog RTL ASIC Design SOC Design CDC Lint Synthesis ECO Python Perl Tcl STA Physical Design GenAI System Architecture +10 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less