Advanced ASIC FPGA Verification Engineer

General Dynamics

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Remote

Quick summary

Work type: Remote
Location: Scottsdale, AZ
Salary: $122,785–$136,215 / yr
Posted: 3 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $130k

$111k $230k

below market most similar roles pay here above market

This role pays less than 93% of similar roles. Most pay $160,212–$216,250 — the blue band above. At the midpoint, this role pays about $130k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1377 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 1184 roles with salary data.

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At a glance

TL;DR · Advanced ASIC FPGA Verification Engineer

Role Posting Log in to save

The Advanced ASIC FPGA Verification Engineer joins the engineering team to lead the definition, design, verification, and documentation of ASIC and FPGA developments. This role involves determining architecture, defining module interfaces, and creating comprehensive test and simulation plans to establish functional criteria. The engineer will build UVM testbenches, develop agents, and utilize bus functional models while performing constrained random testing and functional coverage analysis. Key technologies include SystemVerilog, UVM, and RTL simulation tools like Questa or Modelsim in a Linux environment. Proficiency in Python, TCL, and shell scripting is required, along with experience in AXI, PCIe, and DSP functions. The position solves complex hardware verification problems, ensuring high-speed interfaces and memory designs meet rigorous requirements-based verification strategies for mission-critical systems.

Skills

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa ModelSim Formal Verification AXI PCIe DSP GitLab VHDL Constrained Random Testing Assertions Register Abstraction Layer

What you'll do

Define, design, verify, and document ASIC and FPGA developments.
Determine architecture, system simulation, and detailed design approaches.
Define module interfaces and all aspects of device design and simulation.
Create test and simulation plans that establish functional criteria.
Verify test results and analyze performance metrics.
Develop UVM testbenches for designs implemented in Xilinx devices and SoCs.
Debug FPGA/ASIC hardware and assist with hardware/software integration.
Use scripting languages like Python, TCL, and Shell scripts for automation.

What we're looking for

U.S. citizenship is required.
Must be able to obtain a TS/SCI security clearance within a reasonable amount of time.
Bachelor's degree in Electrical or Computer Engineering, or a related field, with 5+ years of job-related experience.
Master's degree and 3 years of job-related experience in a related field.
In-depth experience using RTL simulation tools like Siemens Mentor Graphics Questa or Modelsim in a Linux environment (preferred).
In-depth knowledge of SystemVerilog, object-oriented programming, and Universal Verification Methodology (UVM) (preferred).
Experience with scripting languages such as Linux shell scripts, TCL, and Python (preferred).
Familiarity with Formal Verification tools, code coverage, and writing waivers (preferred).

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