below marketmost similar roles pay hereabove market
This role pays less than
89%
of similar roles. Most pay
$159,612–$216,250
— the blue band above.
At the midpoint, this role pays about
$136k
versus about
$188k
for comparable roles.
Based on 240 similar postings.
Employer
About General Dynamics
General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.
General Dynamics currently has
1377 open roles
on FindRole.
Listed pay typically runs
$124,093–$150,385
across 1184 roles with salary data.
The Advanced ASIC FPGA Engineer joins a close-knit team of engineers to lead digital design efforts. This role focuses on transitioning designs from interim FPGA platforms to full ASIC implementation in collaboration with a packaging team. Key responsibilities include defining architecture, performing system simulations, and managing the full development life cycle, including synthesis, place and route, and timing analysis. The engineer will mentor others through the conversion process while conducting hardware integration using oscilloscopes, logic analyzers, and JTAG debuggers. Required technical skills include proficiency in VHDL, Microsemi and Xilinx FPGA platforms, and EDA tools like Vivado, Libero, Mentor, and Cadence. The work involves solving complex semiconductor design problems, specifically managing the technical transition from FPGA prototypes to production-ready ASIC hardware.
Lead digital design efforts using VHDL on interim FPGA platforms and transition designs to full ASIC implementation.
Define architecture, module interfaces, system simulations, and detailed design approaches for ASIC and FPGA developments.
Evaluate process flows including high-level design, synthesis, place and route, timing, and power utilization.
Create test and simulation plans to establish functional criteria and verify performance results.
Conduct hardware integration and testing using oscilloscopes, logic analyzers, and JTAG debuggers.
Mentor and guide other engineers through the FPGA-to-ASIC conversion methodology and best practices.
Review vendor capabilities, foundry technologies, device libraries, and simulation tools.
Select components and equipment based on technical specifications and reliability analysis.
What we're looking for
U.S. citizenship is required.
Ability to obtain a Department of Defense Secret security clearance within 18 months.
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology, or Mathematics field plus 5+ years of experience.
Master's degree plus 3 years of job-related experience.
Strong proficiency in VHDL for digital design and simulation.
Hands-on experience with Microsemi and/or Xilinx FPGA development.
Proficiency with Vivado, Libero, Mentor, and/or Cadence EDA tools.
Hardware integration experience with lab tools like oscilloscopes, logic analyzers, and JTAG debuggers.
Ability to mentor others through technical processes.
Active DoD Security Clearance (preferred).
ASIC design or tape-out experience (preferred).
PCB/circuit board design background (preferred).
FPGA-to-ASIC conversion experience (preferred).
Experience with project cost and schedule awareness in a program environment (preferred).
ASIC
FPGA
VHDL
Vivado
Libero
Mentor
Cadence
Xilinx
Microsemi
EDA Tools
Digital Design
Synthesis
Place and Route
power utilization
JTAG
Oscilloscopes
Logic Analyzers
System Simulation
FPGA
ASIC
VHDL
Verilog
C
C++
Xilinx Vivado
Altera Quartus
RTL
Computer Architecture
RISC-V
PCI Express
DDR
Cryptography
Secure Boot
Simulation
Synthesis
Place and Route