ASIC Packaging Signal/Power Integrity Hardware Engineer

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live today
Closes
Nov 27, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $189k
$141k $240k
below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $189k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Packaging Signal/Power Integrity Hardware Engineer

Role Posting Log in to save

The ASIC Packaging Signal/Power Integrity Hardware Engineer joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance silicon devices. This role involves designing, documenting, and verifying packaging to meet power, performance, and area goals for complex networking products. Key responsibilities include implementing design rules for ultra-high-speed signaling, analyzing substrate signal integrity and power integrity, and collaborating with layout teams to optimize interposer, substrate, and PCB solutions. The position requires proficiency in high-speed design theory, including transmission line theory and scattering parameters, applied to 56G PAM4 SerDes architectures. Candidates must use industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, Keysight ADS, and Cadence APD. Technical expertise in 2.5D fanout technologies, HBM, and die-to-die interfaces like UCIe is also required.

Skills

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD SPICE PAM4 SerDes 2.5D Fanout HBM UCIe IBIS Vector Network Analysis Transmission Line Theory Electromagnetics

What you'll do

  • Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
  • Analyze substrate signal integrity (SI) and power integrity (PI) for interposers, substrates, and PCBs.
  • Design and develop ASIC packages for high-volume, high-quality release including post-layout extraction and reporting.
  • Conduct detailed layout reviews and physical design validation to ensure signal performance and crosstalk mitigation.
  • Perform pre- and post-layout SI/PI simulations using industry-standard EDA tools like Cadence Sigrity and Ansys HFSS.
  • Execute circuit-level analysis and signal modeling using SPICE for performance validation.
  • Resolve complex technical issues by applying advanced technology design rules with system partners and vendors.

What we're looking for

  • Must live within commuting distance of the San Jose, CA office and commute 4-5 days per week.
  • Bachelor's in Electrical Engineering with 4+ years of experience, Master's with 2+ years, or PhD with 0+ years of experience.
  • Experience with high-speed design principles including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.
  • Experience with 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
  • Proficiency in pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
  • Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
  • Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity.

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