Advanced ASIC FPGA Verification Engineer

General Dynamics

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Scottsdale, AZ
Salary: $122,785–$136,215 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $130k

$111k $230k

below market most similar roles pay here above market

This role pays less than 93% of similar roles. Most pay $160,212–$216,250 — the blue band above. At the midpoint, this role pays about $130k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1377 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 1184 roles with salary data.

Most-posted roles

View all roles at General Dynamics

At a glance

TL;DR · Advanced ASIC FPGA Verification Engineer

Role Posting Log in to save

The Advanced ASIC FPGA Verification Engineer joins the engineering team to lead the definition, design, verification, and documentation of ASIC and FPGA developments. This role involves determining architecture, creating test and simulation plans, and verifying results to ensure functional criteria are met. You will build UVM testbenches, develop agents, and utilize bus functional models for designs implemented in Xilinx devices and SoCs. Key technologies include SystemVerilog, UVM, and RTL simulation tools like Questa or Modelsim in a Linux environment. You will also use Python, TCL, and shell scripts for automation. Core responsibilities include managing functional coverage, assertions, and formal verification for complex interfaces like AXI, PCIe, and SpaceWire, while solving technical problems related to DSP functions and hardware/software integration.

Skills

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa Modelsim Formal Verification AXI PCIe DSP GitLab Constrained Random Testing Assertions Register Abstraction Layer Xilinx

What you'll do

Define, design, verify, and document ASIC and FPGA developments.
Determine architecture, system simulation, and detailed design approaches.
Define module interfaces and all aspects of device design and simulation.
Create test and simulation plans that establish functional criteria.
Verify test results and analyze performance metrics.
Develop UVM testbenches for designs implemented in Xilinx devices and SoCs.
Debug FPGA/ASIC hardware and assist with hardware/software integration.
Use scripting languages like Python, TCL, and Shell scripts for verification tasks.

What we're looking for

U.S. citizenship is required.
Must be able to obtain a TS/SCI security clearance within a reasonable amount of time.
Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 5+ years of job-related experience.
Master's degree and 3 years of job-related experience is also acceptable.
In-depth experience using RTL simulation tools like Siemens Mentor Graphics Questa or Modelsim in a Linux environment (preferred).
In-depth knowledge of SystemVerilog, object-oriented programming, and Universal Verification Methodology (UVM) (preferred).
Experience with scripting languages such as Linux shell scripts, TCL, or Python (preferred).
Experience with Xilinx devices, IP, SoCs, and AXI protocols (preferred).

Similar roles

Advanced ASIC FPGA Verification Engineer

General Dynamics

Remote (Scottsdale, AZ) 3 days ago $122,785–$136,215

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa ModelSim Formal Verification AXI PCIe DSP GitLab VHDL Constrained Random Testing Assertions Register Abstraction Layer

5+ yrs exp Remote

Save

Advanced ASIC FPGA Engineer

General Dynamics

Scottsdale, AZ 5 days ago $122,785–$136,215

ASIC FPGA Verilog VHDL SystemVerilog Python Tcl Perl Vivado Libero ISE Synplify QuestaSim UVM OVM SVA Digital Design Synthesis Place and Route Timing Closure Clock-Domain-Crossing Logic Analyzer Oscilloscope

5+ yrs exp Hybrid

Save

Senior Advanced ASIC FPGA Engineer

General Dynamics

Remote (Scottsdale, AZ) 3 days ago $152,462–$169,138

ASIC FPGA SystemVerilog Verilog UVM OVM SVA Digital Signal Processing Formal Verification Constrained Random Testing Functional Coverage Synthesis Place and Route Agile Microsoft Office

8+ yrs exp Remote

Save

Senior Principal ASIC FPGA Engineer

General Dynamics

Scottsdale, AZ 18 days ago $182,139–$202,060

ASIC FPGA Synthesis Place and Route Power Utilization System Simulation Microsoft Office AI

10+ yrs exp Hybrid

Save

ASIC Verification Engineer

Nvidia

Austin, TX 4 days ago $116,000–$189,750

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification

2+ yrs exp Hybrid

Save

Senior FPGA Verification Engineer

Anduril Industries

Waltham, MA 11 days ago $191,000–$254,000

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC Python C C++ Perl Unix Linux Git Subversion QuestaSim Synplify Quartus Vivado Constrained-Random Testing Assertion-Based Verification

8+ yrs exp

Save