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UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

Python ASIC Verification CI/CD

Python ASIC Verification CI/CD

Python CI/CD

Python ASIC verification Test bench development

Python ASIC Design Verification Test Bench Development CI/CD

Python ASIC Verification

Python SystemVerilog UVM VCS Verdi Jenkins Make CI/CD Perl Docker Kubernetes Terraform AWS GCP Git GitHub Mercurial SVN Prometheus Grafana AI Machine_Learning +17 more Show less

Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

SystemVerilog UVM VCS Verdi Perl Python C++ UPF DFT Machine_Learning ASIC_design_flow +6 more Show less

SystemVerilog UVM C++ Verilog Linux Windows Python Git CI/CD Jenkins Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Incisive Simulator Formal Verification Random Testing Directed Testing +15 more Show less

SystemVerilog UVM Python Verilog VCS Verdi OOPS CI/CD +3 more Show less