ASIC Design Verification Engineer

Amazon Inc

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Austin, TXSunnyvale, CARedmond, WASan Diego, CA
Salary: $153,600–$215,000 / yr
Posted: 124 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $174k

This role $184k

$135k $224k

below market most similar roles pay here above market

This role pays more than 71% of similar roles. Most pay $160,000–$187,250 — the blue band above. At the midpoint, this role pays about $184k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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The ASIC Design Verification Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and gateways. This role involves defining modems, high-speed interfaces, embedded processors, and DSP solutions using the latest CMOS generation technologies. You will implement a state of the art verification environment to test RTL against reference Matlab and C models, develop detailed test plans, and run regressions to collect coverage matrices. Key responsibilities include validating ASIC implementations in Verilog and SystemVerilog, performing formal verification of complex blocks, and constructing system level test benches. You will utilize UVM, SystemC, DPI-C, and scripting to build highly automated environments. The work focuses on solving wireless communication problems for satellite networks without legacy constraints.

Skills

SystemVerilog UVM Verilog SystemC Matlab C DPI-C Formal Verification RTL DSP CMOS Scripting

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab and C models.
Develop detailed test plans and write tests to run regressions and collect coverage matrices.
Validate ASIC implementations using Verilog and SystemVerilog.
Perform formal verification on complex blocks to ensure functional correctness.
Execute system-level verification using test benches constructed with UVM, SystemC, and DPI-C.
Develop a highly automated environment to run regressions and maintain the database organization.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
5+ years in verification, preferably in communication systems.
2+ years in UVM, C, and scripting.
Must be a U.S. citizen, national, permanent resident, refugee, or granted asylum.
Master's degree in Electrical or Communications Engineering or a related field (preferred).
7+ years in digital verification, preferably in communication systems (preferred).
Familiarity with Matlab, modem design verification, and SystemC or Matlab model development (preferred).
Export control laws and regulations, candidates.

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