ASIC Design Verification Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TXSunnyvale, CARedmond, WASan Diego, CA
Salary: $136,000–$184,000 / yr
Posted: 78 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $179k

This role $160k

$128k most similar roles pay here $213k

This role pays less than 71% of similar roles. Most pay $160,000–$197,750 — the shaded band above. At the midpoint, this role pays about $160k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 457 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 447 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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As an ASIC Design Verification Engineer, Amazon Leo, you will join the sub-team responsible for defining and implementing digital chip SOCs for communication via low Earth orbit satellites and gateways. You will build a state of the art verification environment to test RTL against reference Matlab or C models while developing detailed test plans, running regressions, and collecting coverage matrices. Your daily work involves validating ASIC implementations in Verilog and SystemVerilog, performing formal verification on complex blocks, and utilizing UVM, SystemC, and DPI-C for system level verification. You will also develop highly automated environments to manage regression builds and database organization. This role focuses on the technical challenge of developing modems, high-speed interfaces, embedded processors, and DSP solutions using latest CMOS generation technologies to solve complex wireless communication problems in satellite networks.

Skills

UVM SystemVerilog Verilog SystemC Matlab C DPI-C Formal Verification RTL ASIC Digital Verification Scripting CMOS

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab and C models.
Develop detailed test plans and write tests for the verification process.
Run regressions and collect coverage matrices to report progress to the program.
Validate ASIC implementations using Verilog and SystemVerilog.
Perform formal verification of complex blocks to ensure functional correctness.
Execute system-level verification using test benches constructed with UVM, SystemC, and DPI-C.
Develop a highly automated environment for running regressions and maintaining database organization.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
5+ years of experience in verification, preferably in communication systems.
2+ years of experience in UVM, C, and scripting.
Experience with Verilog/SystemVerilog for ASIC implementation validation.
Proficiency in formal verification techniques for complex blocks.
Experience with SystemC, DPI-C, or Matlab model development and integration.
Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.