ASIC Design Verification Engineer

Amazon Inc

Quick summary

Work type: On-site
Location: San Diego, CASunnyvale, CAAustin, TXRedmond, WA
Salary: $136,000–$184,000 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k

This role $160k

$126k most similar roles pay here $225k

This role pays less than 72% of similar roles. Most pay $158,750–$203,200 — the shaded band above. At the midpoint, this role pays about $160k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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Join Amazon Leo’s cutting-edge team as an ASIC Design Verification Engineer and help define digital chip SOCs for Low Earth Orbit satellite communications. You will build a state-of-the-art verification environment to test RTL against reference models, develop detailed test plans, and run formal verification on complex blocks. Your day-to-day involves working with Verilog/SystemVerilog, UVM, SystemC, and DPI-C to ensure functional correctness and automate regression testing. Ideal candidates have 5+ years in communication systems verification, proficiency in C and scripting, and familiarity with Matlab and formal verification techniques. This role offers a unique chance to work on groundbreaking wireless solutions at the forefront of satellite technology.

Skills

UVM SystemVerilog C Matlab Python DPI-C SystemC Formal verification Verilog VCS DVflow CI/CD

What you'll do

Implement a state-of-the-art verification environment for testing RTL against reference models.
Develop detailed test plans and execute regressions to collect coverage data.
Participate in the validation of ASIC implementations using Verilog/SystemVerilog.
Conduct formal verification on complex blocks to ensure functional correctness.
Work with design teams to perform system-level verification using UVM, SystemC.

What we're looking for

5+ years of experience in ASIC design verification, preferably in communication systems.
Proficient in UVM, C, and scripting languages.
Experience with Verilog/SystemVerilog for validation of ASIC implementations.
Familiarity with formal verification techniques and methodologies.
Ability to develop detailed test plans and automate regression testing environments.
Strong written and verbal communication skills for reporting progress and collaborating across teams.

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