ASIC Design Verification Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$134,500–$201,700 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $168k
$124k $236k
below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $162,000–$216,562 — the blue band above. At the midpoint, this role pays about $168k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

The ASIC Design Verification Engineer joins the ASICS Engineering group to manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. The role involves comprehensive pre-silicon test planning for digital power IPs, including testbench development, coverage development, and assertion model development. Key responsibilities include formal verification, property checking, and deploying power-aware UPF verification flows while developing automation to improve efficiency. Candidates must utilize SystemVerilog-UVM, C++, and Python to verify complex SOC subsystems, caches, and DDR memory protocols. The position requires experience with memory verification VIPs, DDR phy, PASIM simulations, and performance and power verification. This role solves critical technical challenges in digital power IP verification and ensures robust functionality across complex SOC architectures through rigorous pre-silicon and post-silicon debug processes.

What you'll do

  • Develop pre-silicon test plans for digital power IPs.
  • Build testbenches using SystemVerilog-UVM and assertion-based verification technologies.
  • Develop coverage and assertion models for complex SoC subsystems.
  • Perform formal verification and property checking.
  • Deploy and manage power-aware UPF verification flows and methodologies.
  • Create automation tools to improve verification efficiency.
  • Conduct post-silicon debug and support for successful tapeouts.
  • Verify performance and power metrics for SoC components.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field.
  • Minimum 3 years of DV experience using UVM and assertion-based verification technologies.
  • Experience verifying complex SOCs or SOC subsystems, including caches and DDR memory protocols.
  • Experience using memory verification VIPs and exposure to DDR phy.
  • Exposure to firmware/driver development using C++, formal verification, PASIM simulations, and perf and power verification.
  • Exposure to multiple successful tapeouts from conception to post-silicon debug.

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