Senior ASIC Design Verification Engineer

Amazon Inc

Quick summary

Work type
On-site
Location
Sunnyvale, CASan Diego, CA
Salary
$159,200–$215,300 / yr
Posted
2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $179k
This role $187k
$135k most similar roles pay here $224k

This role pays more than 69% of similar roles. Most pay $160,000–$197,750 — the shaded band above. At the midpoint, this role pays about $187k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

As a Senior ASIC Design Verification Engineer at Amazon Leo in the Hardware Development division, you will work closely with the design and communication systems team to develop comprehensive verification strategies. Your day-to-day responsibilities include writing tests in C/C++ for embedded CPUs, developing FPGA and emulation platform tests, and participating in system-level verification using UVM, SystemC, and DPI-C test benches. This role requires expertise in digital verification, particularly within communication systems, with a minimum of 7 years of experience in verification and 5 years working with UVM, C/C++, and scripting languages. Familiarity with Matlab is preferred for additional context-specific tasks. The position involves tackling complex challenges at scale, contributing to the development of cutting-edge hardware solutions for Amazon's innovative devices.

What you'll do

  • Write tests in C/C++ for execution on embedded CPU.
  • Develop verification tests for FPGA and emulation platforms.
  • Participate in system-level verification using UVM test benches.
  • Construct test environments using SystemC and DPI-C.
  • Collaborate with design and communication systems teams.

What we're looking for

  • Bachelor's degree in Computer Science, Engineering, or Electrical Engineering required.
  • At least 7 years of experience in verification, preferably in communication systems.
  • Proficient in UVM, C/C++, and scripting for at least 5 years.
  • Strong background in FPGA and emulation platform testing.
  • Experience working with design and communication systems teams on system-level verification.
  • Familiarity with test benches constructed using UVM, SystemC, and DPI-C.

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