Senior ASIC Design Verification Engineer

Amazon Inc

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CASan Diego, CA
Salary: $159,200–$215,300 / yr
Posted: 78 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $179k

This role $187k

$135k most similar roles pay here $224k

This role pays more than 70% of similar roles. Most pay $160,000–$197,750 — the shaded band above. At the midpoint, this role pays about $187k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 457 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 447 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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Sr. ASIC Design Verification Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communication via Low Earth Orbit satellites and gateways. This role involves building a state of the art verification environment to test RTL against reference Matlab and C models while developing detailed test plans, running regressions, and collecting coverage matrices. The engineer will write tests in C/C++ for embedded CPUs, develop tests for FPGA and emulation platforms, and perform formal verification of complex blocks. Key technical requirements include proficiency in UVM, System C, DPI-C, and scripting languages to facilitate system level verification. The work focuses on the development of modems, high-speed interfaces, embedded processors, and DSP solutions using latest CMOS generation technologies to solve wireless communication challenges for satellite networks without legacy constraints.

Skills

UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab and C models.
Develop detailed test plans, write tests, run regressions, and report coverage metrics.
Write C/C++ code to execute tests on embedded CPUs.
Develop specific test cases for FPGA and emulation platforms.
Perform formal verification of complex blocks to ensure functional correctness.
Execute system-level verification using UVM, System C, and DPI-C test benches.
Build highly automated environments to manage regressions and maintain database organization.

What we're looking for

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
7+ years of experience in verification, preferably in communication systems.
5+ years of experience in UVM, C/C++, and scripting.
Master's degree or Ph.D. in Electrical Engineering or a related field.
10+ years of experience in digital verification, preferably in communication systems.
Familiarity with Matlab and formal verification techniques.
Must be a U.S. citizen, national, permanent resident, or lawfully admitted as a refugee or granted asylum.
Export control laws and regulations, candidates.