Senior ASIC Design Verification Engineer

Amazon Inc

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Sunnyvale, CASan Diego, CA
Salary: $185,200–$250,000 / yr
Posted: 124 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $187k

This role $218k

$138k $262k

below market most similar roles pay here above market

This role pays more than 89% of similar roles. Most pay $161,500–$211,537 — the blue band above. At the midpoint, this role pays about $218k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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The Sr. ASIC Design Verification Engineer joins the Amazon Leo sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and gateways. In this role, you will implement a state of the art verification environment to test RTL against reference Matlab and C models. Daily responsibilities include developing detailed test plans, writing tests in C/C++ for embedded CPUs, and developing tests for FPGA and emulation platforms. You will perform formal verification of complex blocks and participate in system level verification using test benches constructed with UVM, System C, and DPI-C. The work involves defining modems, high-speed interfaces, embedded processors, and DSP solutions using the latest CMOS generation technologies to solve wireless communication problems for satellite networks.

Skills

UVM C/C++ Formal Verification System C DPI-C Matlab RTL FPGA Emulation Scripting DSP CMOS

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab and C models.
Develop detailed test plans, write tests, run regressions, and report coverage matrices to the program.
Write C/C++ tests to execute on embedded CPUs.
Develop specific tests for FPGA and emulation platforms.
Run formal verification on complex blocks to ensure functional correctness.
Participate in system-level verification using test benches constructed with UVM, SystemC, and DPI-C.
Develop a highly automated environment to run regressions and maintain the database organization.

What we're looking for

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
7+ years in verification, preferably in communication systems.
5+ years in UVM, C/C++, and scripting.
Master's degree or Ph.D. degree in Electrical Engineering or related field (preferred).
10+ years in digital verification, preferably in communication systems (preferred).
Familiarity with Matlab (preferred).
U.S. citizen, national, permanent resident, refugee, or granted asylum.
Export control laws and regulations, candidates.

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