Senior ASIC Design Verification Infrastructure and Tools Engineer, GPU

Nvidia

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Remote

Quick summary

Work type
Remote
Location
Santa Clara, CAWestford, MAAustin, TXDurham, NC
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
75 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $197k
This role $177k
$123k $254k
below market most similar roles pay here above market

This role pays less than 62% of similar roles. Most pay $177,250–$217,600 — the blue band above. At the midpoint, this role pays about $177k versus about $197k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Infrastructure and Tools Engineer, GPU

The Senior ASIC Design Verification Infrastructure and Tools Engineer joins the high-speed IO infrastructure team to advance systems that qualify, integrate, and deliver complex ASIC IP across multiple products. This role involves building and improving high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development. Key responsibilities include improving CI reliability, scalability, and debuggability across distributed compute environments while applying practical AI workflows for debug assistance and automation. The engineer will use Verilog, SystemVerilog, Python, and Perl alongside industry tools like VCS, Verdi, and Xcelium. Core tasks involve root-cause analysis of complex infrastructure failures, defining metrics for integration latency and flow health, and collaborating with designers and firmware engineers to solve ambiguous technical problems within the ASIC development lifecycle.

What you'll do

  • Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP.
  • Improve CI reliability, turnaround time, debuggability, and scalability across distributed compute environments.
  • Root-cause complex failures across development, verification, build systems, tools, infrastructure, and compute environments.
  • Apply practical AI workflows for debug assistance, run triage, summarization, documentation, and workflow automation.
  • Turn recurring integration or qualification difficulties into durable automation and process improvements.
  • Define and publish metrics for integration latency, flow health, failure trends, and engineering efficiency.
  • Use metrics to guide engineering priorities, forecast risk, and optimize operational systems.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 5+ years of relevant industry experience.
  • Strong understanding of ASIC development workflows, including builds, simulation, regressions, debug, integration, and qualification.
  • Experience with verification methodology such as UVM or similar.
  • Strong working knowledge of Verilog/SystemVerilog, including RTL development or pre-silicon verification/debug experience.
  • Exposure to industry simulation and debug tools such as VCS, Verdi, Xcelium, or similar.
  • Strong programming skills in Python, Perl, or another scripting/systems programming language.
  • Experience with SystemVerilog and object-oriented verification environments.

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