Senior ASIC Design Verification Infrastructure and Tools Engineer

Nvidia

Confirmed live 2 days ago High trust
Remote

Quick summary

Work type
Remote
Location
Santa Clara, CAWestford, MAAustin, TXDurham, NC
Salary
$136,000–$218,500 / yr
Posted
29 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $177k
$125k most similar roles pay here $241k

This role pays less than 59% of similar roles. Most pay $169,712–$216,562 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Infrastructure and Tools Engineer

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU joins the high-speed IO infrastructure team to advance systems that qualify, integrate, and deliver complex ASIC IP across multiple products. This role focuses on building and improving integration automation, pre-submit qualification flows, build and verification infrastructure, and operational metrics for large-scale ASIC development. You will develop tools to improve CI reliability, turnaround time, and debuggability while applying AI workflows for debug assistance and workflow automation. The position requires expertise in Verilog, SystemVerilog, UVM, and scripting languages like Python or Perl. Candidates must possess experience with simulation and debug tools such as VCS, Verdi, or Xcelium. You will solve complex problems across build systems and compute environments to turn recurring integration difficulties into durable automation while collaborating with designers and firmware engineers to optimize engineering efficiency.

What you'll do

  • Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development.
  • Improve CI reliability, turnaround time, debuggability, and scalability across distributed compute environments.
  • Root-cause complex failures across development, verification, build systems, tools, infrastructure, and compute environments.
  • Convert recurring integration or qualification difficulties into durable automation and process improvements.
  • Define and use metrics for integration latency, flow health, failure trends, and engineering efficiency to guide priorities.
  • Implement practical AI workflows for debug assistance, run triage, summarization, and documentation.
  • Drive ambiguous technical problems to closure by investigating across multiple domains including firmware and methodology.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 5+ years of relevant industry experience.
  • Strong understanding of ASIC development workflows including builds, simulation, regressions, debug, integration, and qualification.
  • Experience with verification methodologies such as UVM or similar.
  • Strong working knowledge of Verilog/SystemVerilog for RTL development or pre-silicon verification and debug.
  • Proficiency in Python, Perl, or other scripting and systems programming languages.
  • Exposure to industry simulation and debug tools like VCS, Verdi, Xcelium, or similar.
  • Experience with SystemVerilog and object-oriented verification environments.

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