ASIC Design Verification Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Rochester, NY
Salary: $144,800–$217,200 / yr
Posted: 70 days ago
Freshness: Confirmed live today
Closes: Aug 18, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k

This role $181k

$135k $235k

below market most similar roles pay here above market

This role pays less than 57% of similar roles. Most pay $162,000–$217,525 — the blue band above. At the midpoint, this role pays about $181k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

Role Posting Log in to save

The ASIC Design Verification Engineer will own the verification strategy, test plan, and coverage closure for a mixed-signal power management IC. Working within a team that spans Analog, Firmware, Systems Engineering, and Architecture, the engineer will drive system-level verification of the full SOC, including boot sequencing, power state transitions, and fault scenarios. Daily tasks involve building and maintaining SystemVerilog and UVM testbench components, sequences, checkers, and assertions. The role requires verifying digital/analog interfaces using real-number models (RNM) and performing firmware/RTL co-simulation. Key technical skills include SystemVerilog RTL design, assertion-based verification (SVA), and regression automation. The position addresses the technical challenge of ensuring mixed-signal power management functionality and silicon intent through rigorous pre-silicon verification and post-silicon bring-up correlation.

Skills

SystemVerilog UVM RTL ASIC Mixed-Signal Verification Real-Number Modeling RNM Verilog-AMS SVA Formal Verification Co-simulation FPGA Prototyping Regression Automation Post-silicon Bring-up Hardware/Software Co-verification

What you'll do

Own the verification strategy, test plan, and coverage closure for a mixed-signal power management IC.
Define functional and code coverage goals and report verification status and readiness to the project team.
Develop and execute system-level verification for the full SOC, including boot sequencing and power state transitions.
Build and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level.
Verify digital/analog interfaces using real-number models (RNM) of analog macros.
Contribute to SystemVerilog RTL design work and perform design reviews with RTL designers.
Support post-silicon bring-up by correlating silicon behavior back to pre-silicon test cases.
Maintain and improve regression infrastructure, triage flows, and results reporting.

What we're looking for

Bachelor's or master's degree in electrical or computer engineering.
Experience owning verification strategy, test plans, and coverage closure for mixed-signal power management ICs (preferred).
Proficiency in SystemVerilog and UVM testbench development, including ownership of verification through tape-out (preferred).
Ability to read and understand RTL and design specifications to independently derive test intent.
Experience with real-number modeling (RNM) of analog blocks in SystemVerilog or Verilog-AMS (preferred).
Experience with firmware/RTL co-simulation or hardware/software co-verification (preferred).
Experience with formal verification, assertion-based verification (SVA), or emulation/FPGA prototyping (preferred).
Experience with post-silicon bring-up, debug, and mentoring engineers (preferred).

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